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Searched refs:QuadSPI_LCKCR_LOCK_MASK (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h799 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
802 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h793 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
796 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h1264 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
1267 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h19115 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
19117 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h20088 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
20090 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h18647 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
18649 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h18645 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
18647 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27981 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
27983 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27982 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
27984 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44654 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
44656 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h46827 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
46829 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h46827 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
46829 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h46827 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
46829 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h46827 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) macro
46829 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h30778 #define QuadSPI_LCKCR_LOCK_MASK 0x1u macro
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37975 #define QuadSPI_LCKCR_LOCK_MASK 0x1u macro