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Searched refs:QuadSPI_IPCR_SEQID_MASK (Results 1 – 17 of 17) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h239 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
242 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h189 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
192 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/
Dfsl_qspi.c408 base->IPCR = ((base->IPCR & (~QuadSPI_IPCR_SEQID_MASK)) | QuadSPI_IPCR_SEQID(index / 4U)); in QSPI_ExecuteIPCommand()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h300 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
303 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18382 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
18384 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19355 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
19357 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h17914 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
17916 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h17912 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
17914 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27366 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
27368 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27367 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
27369 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44130 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
44132 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h46303 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
46305 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h46303 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
46305 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h30534 #define QuadSPI_IPCR_SEQID_MASK 0xF000000u macro
30536 … (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_SEQID_SHIFT))&QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h46303 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
46305 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h46303 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) macro
46305 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37737 #define QuadSPI_IPCR_SEQID_MASK 0xF000000u macro
37739 … (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_SEQID_SHIFT))&QuadSPI_IPCR_SEQID_MASK)