| /hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K148_QUADSPI.h | 619 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
622 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_QUADSPI.h | 637 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
640 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/ |
| D | fsl_qspi.h | 108 kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_QUADSPI.h | 1036 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
1039 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/s32/drivers/s32k3/Fls/src/ |
| D | Qspi_Ip_Controller.c | 171 QuadSPI_FR_ILLINE_MASK | \
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| /hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/src/ |
| D | Qspi_Ip_Controller.c | 171 QuadSPI_FR_ILLINE_MASK | \
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/ |
| D | MK80F25615.h | 18901 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
18903 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/ |
| D | MK82F25615.h | 19874 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
19876 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/ |
| D | MK28FA15.h | 18433 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
18435 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/ |
| D | MK27FA15.h | 18431 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
18433 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/ |
| D | MCIMX7U3_cm4.h | 27758 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
27760 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/ |
| D | MCIMX7U5_cm4.h | 27759 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
27761 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 44439 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
44441 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 46612 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
46614 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 46612 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
46614 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | MIMX8MQ6_cm4.h | 46612 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
46614 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | MIMX8MQ7_cm4.h | 46612 #define QuadSPI_FR_ILLINE_MASK (0x800000U) macro
46614 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
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| /hal_nxp-latest/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 30697 #define QuadSPI_FR_ILLINE_MASK 0x800000u macro
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| /hal_nxp-latest/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 37896 #define QuadSPI_FR_ILLINE_MASK 0x800000u macro
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