Home
last modified time | relevance | path

Searched refs:QuadSPI_FLSHCR_TDH_MASK (Results 1 – 17 of 17) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h258 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) macro
261 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
/hal_nxp-latest/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h534 #ifdef QuadSPI_FLSHCR_TDH_MASK
544 RegValue &= (uint32)(~(QuadSPI_FLSHCR_TDH_MASK)); in Qspi_Ip_SetDataInHoldTime()
/hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/include/
DQspi_Ip_HwAccess.h824 #ifdef QuadSPI_FLSHCR_TDH_MASK
832 RegValue &= (uint32)(~(QuadSPI_FLSHCR_TDH_MASK)); in Qspi_Ip_SetDataInHoldTime()
/hal_nxp-latest/s32/drivers/s32k3/Fls/src/
DQspi_Ip_Controller.c1013 #ifdef QuadSPI_FLSHCR_TDH_MASK in Qspi_Ip_ConfigureReadOptions()
1023 #ifdef QuadSPI_FLSHCR_TDH_MASK in Qspi_Ip_ConfigureReadOptions()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h319 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) macro
322 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18395 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) macro
18402 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19368 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) macro
19375 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h17927 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) macro
17934 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h17925 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) macro
17932 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27382 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) macro
27389 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27383 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) macro
27390 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44146 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) macro
44154 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h46319 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) macro
46327 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h46319 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) macro
46327 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h46319 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) macro
46327 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h46319 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) macro
46327 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37747 #define QuadSPI_FLSHCR_TDH_MASK 0x30000u macro
37749 … (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TDH_SHIFT))&QuadSPI_FLSHCR_TDH_MASK)