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Searched refs:QuadSPI_DLLSR_DLLB_FINE_UNDERFLOW_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h774 #define QuadSPI_DLLSR_DLLB_FINE_UNDERFLOW_MASK (0x10000000U) macro
777 …int32_t)(x)) << QuadSPI_DLLSR_DLLB_FINE_UNDERFLOW_SHIFT)) & QuadSPI_DLLSR_DLLB_FINE_UNDERFLOW_MASK)
/hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/include/
DQspi_Ip_HwAccess.h755 …RegValue = RegValue & (QuadSPI_DLLSR_DLLB_RANGE_ERR_MASK | QuadSPI_DLLSR_DLLB_FINE_UNDERFLOW_MASK); in Qspi_Ip_DLLGetErrorStatusB()