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Searched refs:QuadSPI_BUF2IND_TPINDX2_MASK (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h369 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) macro
372 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h309 #define QuadSPI_BUF2IND_TPINDX2_MASK (0x1F8U) macro
312 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h435 #define QuadSPI_BUF2IND_TPINDX2_MASK (0x7F8U) macro
438 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18683 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) macro
18685 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19656 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) macro
19658 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h18215 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) macro
18217 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h18213 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) macro
18215 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27487 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) macro
27489 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27488 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) macro
27490 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44244 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) macro
44246 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h46417 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) macro
46419 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h46417 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) macro
46419 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h30591 #define QuadSPI_BUF2IND_TPINDX2_MASK 0xFFFFFFF8u macro
30593 … (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2IND_TPINDX2_SHIFT))&QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h46417 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) macro
46419 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h46417 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) macro
46419 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37797 #define QuadSPI_BUF2IND_TPINDX2_MASK 0xFFFFFFF8u macro
37799 … (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2IND_TPINDX2_SHIFT))&QuadSPI_BUF2IND_TPINDX2_MASK)