1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_QUEUE_DESCRIPTOR.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_QUEUE_DESCRIPTOR 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_QUEUE_DESCRIPTOR_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_QUEUE_DESCRIPTOR_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- QUEUE_DESCRIPTOR Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup QUEUE_DESCRIPTOR_Peripheral_Access_Layer QUEUE_DESCRIPTOR Peripheral Access Layer 68 * @{ 69 */ 70 71 /** QUEUE_DESCRIPTOR - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t QPUSH_DSC_CFG; /**< QPUSH DSC CFG, offset: 0x0 */ 74 __IO uint32_t QPUSH_DSC_SRCP; /**< QPUSH DSC SRCP, offset: 0x4 */ 75 __IO uint32_t QPUSH_DSC_DSTP; /**< QPUSH DSC DSTP, offset: 0x8 */ 76 __IO uint32_t QPUSH_DSC_DMASZ; /**< QPUSH DSC DMASZ, offset: 0xC */ 77 __IO uint32_t QPUSH_DSC_SRC; /**< QPUSH DSC SRC, offset: 0x10 */ 78 __IO uint32_t QPUSH_DSC_LINE; /**< QPUSH DSC LINE, offset: 0x14 */ 79 __IO uint32_t QPUSH_DSC_DST; /**< QPUSH DSC DST, offset: 0x18 */ 80 __IO uint32_t QPUSH_DSC_HGHT; /**< QPUSH DSC HGHT, offset: 0x1C */ 81 __IO uint32_t QPUSH_NUM; /**< QPUSH NUM, offset: 0x20 */ 82 } QUEUE_DESCRIPTOR_Type, *QUEUE_DESCRIPTOR_MemMapPtr; 83 84 /** Number of instances of the QUEUE_DESCRIPTOR module. */ 85 #define QUEUE_DESCRIPTOR_INSTANCE_COUNT (1u) 86 87 /* QUEUE_DESCRIPTOR - Peripheral instance base addresses */ 88 /** Peripheral CEVA_SPF2__QUEUE_DESCRIPTOR base address */ 89 #define IP_CEVA_SPF2__QUEUE_DESCRIPTOR_BASE (0x24401100u) 90 /** Peripheral CEVA_SPF2__QUEUE_DESCRIPTOR base pointer */ 91 #define IP_CEVA_SPF2__QUEUE_DESCRIPTOR ((QUEUE_DESCRIPTOR_Type *)IP_CEVA_SPF2__QUEUE_DESCRIPTOR_BASE) 92 /** Array initializer of QUEUE_DESCRIPTOR peripheral base addresses */ 93 #define IP_QUEUE_DESCRIPTOR_BASE_ADDRS { IP_CEVA_SPF2__QUEUE_DESCRIPTOR_BASE } 94 /** Array initializer of QUEUE_DESCRIPTOR peripheral base pointers */ 95 #define IP_QUEUE_DESCRIPTOR_BASE_PTRS { IP_CEVA_SPF2__QUEUE_DESCRIPTOR } 96 97 /* ---------------------------------------------------------------------------- 98 -- QUEUE_DESCRIPTOR Register Masks 99 ---------------------------------------------------------------------------- */ 100 101 /*! 102 * @addtogroup QUEUE_DESCRIPTOR_Register_Masks QUEUE_DESCRIPTOR Register Masks 103 * @{ 104 */ 105 106 /*! @name QPUSH_DSC_CFG - QPUSH DSC CFG */ 107 /*! @{ */ 108 109 #define QUEUE_DESCRIPTOR_QPUSH_DSC_CFG_QPUSH_DSC_CFG_MASK (0xFFFFFFFFU) 110 #define QUEUE_DESCRIPTOR_QPUSH_DSC_CFG_QPUSH_DSC_CFG_SHIFT (0U) 111 #define QUEUE_DESCRIPTOR_QPUSH_DSC_CFG_QPUSH_DSC_CFG_WIDTH (32U) 112 #define QUEUE_DESCRIPTOR_QPUSH_DSC_CFG_QPUSH_DSC_CFG(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_DESCRIPTOR_QPUSH_DSC_CFG_QPUSH_DSC_CFG_SHIFT)) & QUEUE_DESCRIPTOR_QPUSH_DSC_CFG_QPUSH_DSC_CFG_MASK) 113 /*! @} */ 114 115 /*! @name QPUSH_DSC_SRCP - QPUSH DSC SRCP */ 116 /*! @{ */ 117 118 #define QUEUE_DESCRIPTOR_QPUSH_DSC_SRCP_QPUSH_DSC_SRCP_MASK (0xFFFFFFFFU) 119 #define QUEUE_DESCRIPTOR_QPUSH_DSC_SRCP_QPUSH_DSC_SRCP_SHIFT (0U) 120 #define QUEUE_DESCRIPTOR_QPUSH_DSC_SRCP_QPUSH_DSC_SRCP_WIDTH (32U) 121 #define QUEUE_DESCRIPTOR_QPUSH_DSC_SRCP_QPUSH_DSC_SRCP(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_DESCRIPTOR_QPUSH_DSC_SRCP_QPUSH_DSC_SRCP_SHIFT)) & QUEUE_DESCRIPTOR_QPUSH_DSC_SRCP_QPUSH_DSC_SRCP_MASK) 122 /*! @} */ 123 124 /*! @name QPUSH_DSC_DSTP - QPUSH DSC DSTP */ 125 /*! @{ */ 126 127 #define QUEUE_DESCRIPTOR_QPUSH_DSC_DSTP_QPUSH_DSC_DSTP_MASK (0xFFFFFFFFU) 128 #define QUEUE_DESCRIPTOR_QPUSH_DSC_DSTP_QPUSH_DSC_DSTP_SHIFT (0U) 129 #define QUEUE_DESCRIPTOR_QPUSH_DSC_DSTP_QPUSH_DSC_DSTP_WIDTH (32U) 130 #define QUEUE_DESCRIPTOR_QPUSH_DSC_DSTP_QPUSH_DSC_DSTP(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_DESCRIPTOR_QPUSH_DSC_DSTP_QPUSH_DSC_DSTP_SHIFT)) & QUEUE_DESCRIPTOR_QPUSH_DSC_DSTP_QPUSH_DSC_DSTP_MASK) 131 /*! @} */ 132 133 /*! @name QPUSH_DSC_DMASZ - QPUSH DSC DMASZ */ 134 /*! @{ */ 135 136 #define QUEUE_DESCRIPTOR_QPUSH_DSC_DMASZ_QPUSH_DSC_DMASZ_MASK (0xFFFFFFFFU) 137 #define QUEUE_DESCRIPTOR_QPUSH_DSC_DMASZ_QPUSH_DSC_DMASZ_SHIFT (0U) 138 #define QUEUE_DESCRIPTOR_QPUSH_DSC_DMASZ_QPUSH_DSC_DMASZ_WIDTH (32U) 139 #define QUEUE_DESCRIPTOR_QPUSH_DSC_DMASZ_QPUSH_DSC_DMASZ(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_DESCRIPTOR_QPUSH_DSC_DMASZ_QPUSH_DSC_DMASZ_SHIFT)) & QUEUE_DESCRIPTOR_QPUSH_DSC_DMASZ_QPUSH_DSC_DMASZ_MASK) 140 /*! @} */ 141 142 /*! @name QPUSH_DSC_SRC - QPUSH DSC SRC */ 143 /*! @{ */ 144 145 #define QUEUE_DESCRIPTOR_QPUSH_DSC_SRC_QPUSH_DSC_SRC_MASK (0xFFFFFFFFU) 146 #define QUEUE_DESCRIPTOR_QPUSH_DSC_SRC_QPUSH_DSC_SRC_SHIFT (0U) 147 #define QUEUE_DESCRIPTOR_QPUSH_DSC_SRC_QPUSH_DSC_SRC_WIDTH (32U) 148 #define QUEUE_DESCRIPTOR_QPUSH_DSC_SRC_QPUSH_DSC_SRC(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_DESCRIPTOR_QPUSH_DSC_SRC_QPUSH_DSC_SRC_SHIFT)) & QUEUE_DESCRIPTOR_QPUSH_DSC_SRC_QPUSH_DSC_SRC_MASK) 149 /*! @} */ 150 151 /*! @name QPUSH_DSC_LINE - QPUSH DSC LINE */ 152 /*! @{ */ 153 154 #define QUEUE_DESCRIPTOR_QPUSH_DSC_LINE_QPUSH_DSC_LINE_MASK (0xFFFFFFFFU) 155 #define QUEUE_DESCRIPTOR_QPUSH_DSC_LINE_QPUSH_DSC_LINE_SHIFT (0U) 156 #define QUEUE_DESCRIPTOR_QPUSH_DSC_LINE_QPUSH_DSC_LINE_WIDTH (32U) 157 #define QUEUE_DESCRIPTOR_QPUSH_DSC_LINE_QPUSH_DSC_LINE(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_DESCRIPTOR_QPUSH_DSC_LINE_QPUSH_DSC_LINE_SHIFT)) & QUEUE_DESCRIPTOR_QPUSH_DSC_LINE_QPUSH_DSC_LINE_MASK) 158 /*! @} */ 159 160 /*! @name QPUSH_DSC_DST - QPUSH DSC DST */ 161 /*! @{ */ 162 163 #define QUEUE_DESCRIPTOR_QPUSH_DSC_DST_QPUSH_DSC_DST_MASK (0xFFFFFFFFU) 164 #define QUEUE_DESCRIPTOR_QPUSH_DSC_DST_QPUSH_DSC_DST_SHIFT (0U) 165 #define QUEUE_DESCRIPTOR_QPUSH_DSC_DST_QPUSH_DSC_DST_WIDTH (32U) 166 #define QUEUE_DESCRIPTOR_QPUSH_DSC_DST_QPUSH_DSC_DST(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_DESCRIPTOR_QPUSH_DSC_DST_QPUSH_DSC_DST_SHIFT)) & QUEUE_DESCRIPTOR_QPUSH_DSC_DST_QPUSH_DSC_DST_MASK) 167 /*! @} */ 168 169 /*! @name QPUSH_DSC_HGHT - QPUSH DSC HGHT */ 170 /*! @{ */ 171 172 #define QUEUE_DESCRIPTOR_QPUSH_DSC_HGHT_QPUSH_DSC_HGHT_MASK (0xFFFFFFFFU) 173 #define QUEUE_DESCRIPTOR_QPUSH_DSC_HGHT_QPUSH_DSC_HGHT_SHIFT (0U) 174 #define QUEUE_DESCRIPTOR_QPUSH_DSC_HGHT_QPUSH_DSC_HGHT_WIDTH (32U) 175 #define QUEUE_DESCRIPTOR_QPUSH_DSC_HGHT_QPUSH_DSC_HGHT(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_DESCRIPTOR_QPUSH_DSC_HGHT_QPUSH_DSC_HGHT_SHIFT)) & QUEUE_DESCRIPTOR_QPUSH_DSC_HGHT_QPUSH_DSC_HGHT_MASK) 176 /*! @} */ 177 178 /*! @name QPUSH_NUM - QPUSH NUM */ 179 /*! @{ */ 180 181 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_NUM_MASK (0x1FU) 182 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_NUM_SHIFT (0U) 183 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_NUM_WIDTH (5U) 184 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_NUM(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_NUM_SHIFT)) & QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_NUM_MASK) 185 186 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_AUTO_INC_MASK (0x40U) 187 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_AUTO_INC_SHIFT (6U) 188 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_AUTO_INC_WIDTH (1U) 189 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_AUTO_INC(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_AUTO_INC_SHIFT)) & QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_AUTO_INC_MASK) 190 191 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_STATUS_RLS_MASK (0x10000U) 192 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_STATUS_RLS_SHIFT (16U) 193 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_STATUS_RLS_WIDTH (1U) 194 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_STATUS_RLS(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_STATUS_RLS_SHIFT)) & QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_STATUS_RLS_MASK) 195 196 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_STATUS_MASK (0x20000U) 197 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_STATUS_SHIFT (17U) 198 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_STATUS_WIDTH (1U) 199 #define QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_STATUS(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_STATUS_SHIFT)) & QUEUE_DESCRIPTOR_QPUSH_NUM_QPUSH_STATUS_MASK) 200 /*! @} */ 201 202 /*! 203 * @} 204 */ /* end of group QUEUE_DESCRIPTOR_Register_Masks */ 205 206 /*! 207 * @} 208 */ /* end of group QUEUE_DESCRIPTOR_Peripheral_Access_Layer */ 209 210 #endif /* #if !defined(S32Z2_QUEUE_DESCRIPTOR_H_) */ 211
