1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_DATA_MEMORY_SUBSYSTEM.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_DATA_MEMORY_SUBSYSTEM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_DATA_MEMORY_SUBSYSTEM_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_DATA_MEMORY_SUBSYSTEM_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DATA_MEMORY_SUBSYSTEM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DATA_MEMORY_SUBSYSTEM_Peripheral_Access_Layer DATA_MEMORY_SUBSYSTEM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DATA_MEMORY_SUBSYSTEM - Size of Registers Arrays */ 72 #define DATA_MEMORY_SUBSYSTEM_QMAN_TASK_IDX_COUNT 4u 73 74 /** DATA_MEMORY_SUBSYSTEM - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t MSS_DMBA; /**< IDM Base Address, offset: 0x0 */ 77 __I uint32_t MSS_DMBE; /**< DMSS Idle Indication, offset: 0x4 */ 78 uint8_t RESERVED_0[20]; 79 __I uint32_t MSS_HDCFG; /**< DMSS Hardware Configuration, offset: 0x1C */ 80 uint8_t RESERVED_1[4]; 81 __IO uint32_t MSS_GPOUT; /**< MSS General Purpose 2, offset: 0x24 */ 82 __IO uint32_t MSS_DACC; /**< DDMA Access Configuration, offset: 0x28 */ 83 __IO uint32_t MSS_SDCFG; /**< MSS SW Configuration, offset: 0x2C */ 84 uint8_t RESERVED_2[8]; 85 __IO uint32_t MSS_BARRIER; /**< MSS Memory Barrier Control, offset: 0x38 */ 86 __I uint32_t D_DMAB; /**< DDMA Status, offset: 0x3C */ 87 uint8_t RESERVED_3[4]; 88 __IO uint32_t DBG_WRC0; /**< EDP Write Response Counter, offset: 0x44 */ 89 uint8_t RESERVED_4[16]; 90 __IO uint32_t MSS_DDTC; /**< DDMA Linear Transfer Size, offset: 0x58 */ 91 uint8_t RESERVED_5[4]; 92 __IO uint32_t MSS_2DCFG1; /**< DDMA Configuration 1, offset: 0x60 */ 93 __IO uint32_t MSS_2DCFG2; /**< DDMA Configuration 2, offset: 0x64 */ 94 __IO uint32_t MSS_2DCFG3; /**< DDMA Configuration 3, offset: 0x68 */ 95 __IO uint32_t MSS_2DCFG4; /**< DDMA Configuration 4, offset: 0x6C */ 96 __IO uint32_t MSS_2DCFG5; /**< DDMA Configuration 5, offset: 0x70 */ 97 __IO uint32_t MSS_2DCFG6; /**< DDMA Configuration 6, offset: 0x74 */ 98 __IO uint32_t MSS_DDQS; /**< DDMA Status, offset: 0x78 */ 99 uint8_t RESERVED_6[4]; 100 __IO uint32_t MSS_DDEA; /**< DDMA Address 1, offset: 0x80 */ 101 __IO uint32_t MSS_DDIA; /**< DDMA Address 2, offset: 0x84 */ 102 uint8_t RESERVED_7[4]; 103 __IO uint32_t MSS_DDCL; /**< DDMA Control, offset: 0x8C */ 104 __IO uint32_t DDMA_PAUSE; /**< DDMA Pause Control, offset: 0x90 */ 105 uint8_t RESERVED_8[12]; 106 __I uint32_t MSS_DDESC_ID; /**< DDMA Interrupt Source, offset: 0xA0 */ 107 __IO uint32_t MSS_DDESC_OV; /**< DDMA Task ID Overwrite Indication, offset: 0xA4 */ 108 __I uint32_t MSTR_TASK_ID; /**< DDMA Task (Master) ID, offset: 0xA8 */ 109 uint8_t RESERVED_9[4]; 110 __I uint32_t QMAN_TASK_IDX[DATA_MEMORY_SUBSYSTEM_QMAN_TASK_IDX_COUNT]; /**< QMAN Task IDx, array offset: 0xB0, array step: 0x4 */ 111 } DATA_MEMORY_SUBSYSTEM_Type, *DATA_MEMORY_SUBSYSTEM_MemMapPtr; 112 113 /** Number of instances of the DATA_MEMORY_SUBSYSTEM module. */ 114 #define DATA_MEMORY_SUBSYSTEM_INSTANCE_COUNT (1u) 115 116 /* DATA_MEMORY_SUBSYSTEM - Peripheral instance base addresses */ 117 /** Peripheral CEVA_SPF2__DATA_MEMORY_SUBSYSTEM base address */ 118 #define IP_CEVA_SPF2__DATA_MEMORY_SUBSYSTEM_BASE (0x24400600u) 119 /** Peripheral CEVA_SPF2__DATA_MEMORY_SUBSYSTEM base pointer */ 120 #define IP_CEVA_SPF2__DATA_MEMORY_SUBSYSTEM ((DATA_MEMORY_SUBSYSTEM_Type *)IP_CEVA_SPF2__DATA_MEMORY_SUBSYSTEM_BASE) 121 /** Array initializer of DATA_MEMORY_SUBSYSTEM peripheral base addresses */ 122 #define IP_DATA_MEMORY_SUBSYSTEM_BASE_ADDRS { IP_CEVA_SPF2__DATA_MEMORY_SUBSYSTEM_BASE } 123 /** Array initializer of DATA_MEMORY_SUBSYSTEM peripheral base pointers */ 124 #define IP_DATA_MEMORY_SUBSYSTEM_BASE_PTRS { IP_CEVA_SPF2__DATA_MEMORY_SUBSYSTEM } 125 126 /* ---------------------------------------------------------------------------- 127 -- DATA_MEMORY_SUBSYSTEM Register Masks 128 ---------------------------------------------------------------------------- */ 129 130 /*! 131 * @addtogroup DATA_MEMORY_SUBSYSTEM_Register_Masks DATA_MEMORY_SUBSYSTEM Register Masks 132 * @{ 133 */ 134 135 /*! @name MSS_DMBA - IDM Base Address */ 136 /*! @{ */ 137 138 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBA_DMBA_MASK (0xFFFFFFFFU) 139 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBA_DMBA_SHIFT (0U) 140 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBA_DMBA_WIDTH (32U) 141 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBA_DMBA(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DMBA_DMBA_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DMBA_DMBA_MASK) 142 /*! @} */ 143 144 /*! @name MSS_DMBE - DMSS Idle Indication */ 145 /*! @{ */ 146 147 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_WBE_MASK (0x1U) 148 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_WBE_SHIFT (0U) 149 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_WBE_WIDTH (1U) 150 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_WBE(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DMBE_WBE_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DMBE_WBE_MASK) 151 152 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_EWBE_MASK (0x2U) 153 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_EWBE_SHIFT (1U) 154 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_EWBE_WIDTH (1U) 155 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_EWBE(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DMBE_EWBE_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DMBE_EWBE_MASK) 156 157 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_EDPE_MASK (0x4U) 158 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_EDPE_SHIFT (2U) 159 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_EDPE_WIDTH (1U) 160 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_EDPE(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DMBE_EDPE_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DMBE_EDPE_MASK) 161 162 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_DMSS_IDLE_MASK (0x8U) 163 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_DMSS_IDLE_SHIFT (3U) 164 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_DMSS_IDLE_WIDTH (1U) 165 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_DMSS_IDLE(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DMBE_DMSS_IDLE_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DMBE_DMSS_IDLE_MASK) 166 167 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_ADLB_MASK (0x10U) 168 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_ADLB_SHIFT (4U) 169 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_ADLB_WIDTH (1U) 170 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_ADLB(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DMBE_ADLB_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DMBE_ADLB_MASK) 171 172 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_AXIP_MASK (0x80U) 173 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_AXIP_SHIFT (7U) 174 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_AXIP_WIDTH (1U) 175 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_AXIP(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DMBE_AXIP_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DMBE_AXIP_MASK) 176 177 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_DMA_MASK (0x100U) 178 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_DMA_SHIFT (8U) 179 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_DMA_WIDTH (1U) 180 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_DMA(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DMBE_DMA_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DMBE_DMA_MASK) 181 182 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_QMAN_MASK (0x200U) 183 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_QMAN_SHIFT (9U) 184 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_QMAN_WIDTH (1U) 185 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_QMAN(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DMBE_QMAN_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DMBE_QMAN_MASK) 186 187 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_L1WBB_MASK (0x10000U) 188 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_L1WBB_SHIFT (16U) 189 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_L1WBB_WIDTH (1U) 190 #define DATA_MEMORY_SUBSYSTEM_MSS_DMBE_L1WBB(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DMBE_L1WBB_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DMBE_L1WBB_MASK) 191 /*! @} */ 192 193 /*! @name MSS_HDCFG - DMSS Hardware Configuration */ 194 /*! @{ */ 195 196 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_BLK_NUM_MASK (0x1U) 197 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_BLK_NUM_SHIFT (0U) 198 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_BLK_NUM_WIDTH (1U) 199 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_BLK_NUM(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_BLK_NUM_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_BLK_NUM_MASK) 200 201 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_BNK_NUM_MASK (0x2U) 202 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_BNK_NUM_SHIFT (1U) 203 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_BNK_NUM_WIDTH (1U) 204 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_BNK_NUM(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_BNK_NUM_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_BNK_NUM_MASK) 205 206 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_TCM_SIZE_MASK (0x1CU) 207 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_TCM_SIZE_SHIFT (2U) 208 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_TCM_SIZE_WIDTH (3U) 209 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_TCM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_TCM_SIZE_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_TCM_SIZE_MASK) 210 211 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_EDAP_AXI_WID_MASK (0x20U) 212 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_EDAP_AXI_WID_SHIFT (5U) 213 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_EDAP_AXI_WID_WIDTH (1U) 214 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_EDAP_AXI_WID(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_EDAP_AXI_WID_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_EDAP_AXI_WID_MASK) 215 216 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_EDP_AXI_WID_MASK (0x180U) 217 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_EDP_AXI_WID_SHIFT (7U) 218 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_EDP_AXI_WID_WIDTH (2U) 219 #define DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_EDP_AXI_WID(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_EDP_AXI_WID_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_HDCFG_EDP_AXI_WID_MASK) 220 /*! @} */ 221 222 /*! @name MSS_GPOUT - MSS General Purpose 2 */ 223 /*! @{ */ 224 225 #define DATA_MEMORY_SUBSYSTEM_MSS_GPOUT_GPOUT_MASK (0xFFFFFFFFU) 226 #define DATA_MEMORY_SUBSYSTEM_MSS_GPOUT_GPOUT_SHIFT (0U) 227 #define DATA_MEMORY_SUBSYSTEM_MSS_GPOUT_GPOUT_WIDTH (32U) 228 #define DATA_MEMORY_SUBSYSTEM_MSS_GPOUT_GPOUT(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_GPOUT_GPOUT_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_GPOUT_GPOUT_MASK) 229 /*! @} */ 230 231 /*! @name MSS_DACC - DDMA Access Configuration */ 232 /*! @{ */ 233 234 #define DATA_MEMORY_SUBSYSTEM_MSS_DACC_DOL_MASK (0xF0U) 235 #define DATA_MEMORY_SUBSYSTEM_MSS_DACC_DOL_SHIFT (4U) 236 #define DATA_MEMORY_SUBSYSTEM_MSS_DACC_DOL_WIDTH (4U) 237 #define DATA_MEMORY_SUBSYSTEM_MSS_DACC_DOL(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DACC_DOL_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DACC_DOL_MASK) 238 239 #define DATA_MEMORY_SUBSYSTEM_MSS_DACC_UOL_MASK (0x700U) 240 #define DATA_MEMORY_SUBSYSTEM_MSS_DACC_UOL_SHIFT (8U) 241 #define DATA_MEMORY_SUBSYSTEM_MSS_DACC_UOL_WIDTH (3U) 242 #define DATA_MEMORY_SUBSYSTEM_MSS_DACC_UOL(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DACC_UOL_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DACC_UOL_MASK) 243 /*! @} */ 244 245 /*! @name MSS_SDCFG - MSS SW Configuration */ 246 /*! @{ */ 247 248 #define DATA_MEMORY_SUBSYSTEM_MSS_SDCFG_DAPE_MASK (0x400000U) 249 #define DATA_MEMORY_SUBSYSTEM_MSS_SDCFG_DAPE_SHIFT (22U) 250 #define DATA_MEMORY_SUBSYSTEM_MSS_SDCFG_DAPE_WIDTH (1U) 251 #define DATA_MEMORY_SUBSYSTEM_MSS_SDCFG_DAPE(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_SDCFG_DAPE_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_SDCFG_DAPE_MASK) 252 253 #define DATA_MEMORY_SUBSYSTEM_MSS_SDCFG_EDAP_DS_MASK (0x2000000U) 254 #define DATA_MEMORY_SUBSYSTEM_MSS_SDCFG_EDAP_DS_SHIFT (25U) 255 #define DATA_MEMORY_SUBSYSTEM_MSS_SDCFG_EDAP_DS_WIDTH (1U) 256 #define DATA_MEMORY_SUBSYSTEM_MSS_SDCFG_EDAP_DS(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_SDCFG_EDAP_DS_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_SDCFG_EDAP_DS_MASK) 257 /*! @} */ 258 259 /*! @name MSS_BARRIER - MSS Memory Barrier Control */ 260 /*! @{ */ 261 262 #define DATA_MEMORY_SUBSYSTEM_MSS_BARRIER_INT_ACT_MASK (0x80U) 263 #define DATA_MEMORY_SUBSYSTEM_MSS_BARRIER_INT_ACT_SHIFT (7U) 264 #define DATA_MEMORY_SUBSYSTEM_MSS_BARRIER_INT_ACT_WIDTH (1U) 265 #define DATA_MEMORY_SUBSYSTEM_MSS_BARRIER_INT_ACT(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_BARRIER_INT_ACT_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_BARRIER_INT_ACT_MASK) 266 /*! @} */ 267 268 /*! @name D_DMAB - DDMA Status */ 269 /*! @{ */ 270 271 #define DATA_MEMORY_SUBSYSTEM_D_DMAB_Reserved0_MASK (0x1U) 272 #define DATA_MEMORY_SUBSYSTEM_D_DMAB_Reserved0_SHIFT (0U) 273 #define DATA_MEMORY_SUBSYSTEM_D_DMAB_Reserved0_WIDTH (1U) 274 #define DATA_MEMORY_SUBSYSTEM_D_DMAB_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_D_DMAB_Reserved0_SHIFT)) & DATA_MEMORY_SUBSYSTEM_D_DMAB_Reserved0_MASK) 275 /*! @} */ 276 277 /*! @name DBG_WRC0 - EDP Write Response Counter */ 278 /*! @{ */ 279 280 #define DATA_MEMORY_SUBSYSTEM_DBG_WRC0_WRC0_MASK (0x7FU) 281 #define DATA_MEMORY_SUBSYSTEM_DBG_WRC0_WRC0_SHIFT (0U) 282 #define DATA_MEMORY_SUBSYSTEM_DBG_WRC0_WRC0_WIDTH (7U) 283 #define DATA_MEMORY_SUBSYSTEM_DBG_WRC0_WRC0(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_DBG_WRC0_WRC0_SHIFT)) & DATA_MEMORY_SUBSYSTEM_DBG_WRC0_WRC0_MASK) 284 285 #define DATA_MEMORY_SUBSYSTEM_DBG_WRC0_MAX_OS0_MASK (0x180U) 286 #define DATA_MEMORY_SUBSYSTEM_DBG_WRC0_MAX_OS0_SHIFT (7U) 287 #define DATA_MEMORY_SUBSYSTEM_DBG_WRC0_MAX_OS0_WIDTH (2U) 288 #define DATA_MEMORY_SUBSYSTEM_DBG_WRC0_MAX_OS0(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_DBG_WRC0_MAX_OS0_SHIFT)) & DATA_MEMORY_SUBSYSTEM_DBG_WRC0_MAX_OS0_MASK) 289 /*! @} */ 290 291 /*! @name MSS_DDTC - DDMA Linear Transfer Size */ 292 /*! @{ */ 293 294 #define DATA_MEMORY_SUBSYSTEM_MSS_DDTC_DDTC_MASK (0x3FFFFFU) 295 #define DATA_MEMORY_SUBSYSTEM_MSS_DDTC_DDTC_SHIFT (0U) 296 #define DATA_MEMORY_SUBSYSTEM_MSS_DDTC_DDTC_WIDTH (22U) 297 #define DATA_MEMORY_SUBSYSTEM_MSS_DDTC_DDTC(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDTC_DDTC_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDTC_DDTC_MASK) 298 /*! @} */ 299 300 /*! @name MSS_2DCFG1 - DDMA Configuration 1 */ 301 /*! @{ */ 302 303 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_TDT_MASK (0x1U) 304 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_TDT_SHIFT (0U) 305 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_TDT_WIDTH (1U) 306 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_TDT(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_TDT_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_TDT_MASK) 307 308 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_CLIP_EN_MASK (0xCU) 309 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_CLIP_EN_SHIFT (2U) 310 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_CLIP_EN_WIDTH (2U) 311 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_CLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_CLIP_EN_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_CLIP_EN_MASK) 312 313 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_TRTYP_MASK (0x70U) 314 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_TRTYP_SHIFT (4U) 315 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_TRTYP_WIDTH (3U) 316 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_TRTYP(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_TRTYP_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_TRTYP_MASK) 317 318 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_UNPACK_MASK (0xF00U) 319 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_UNPACK_SHIFT (8U) 320 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_UNPACK_WIDTH (4U) 321 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_UNPACK(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_UNPACK_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_UNPACK_MASK) 322 323 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_ELEMENT_SZ_MASK (0x3000U) 324 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_ELEMENT_SZ_SHIFT (12U) 325 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_ELEMENT_SZ_WIDTH (2U) 326 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_ELEMENT_SZ(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_ELEMENT_SZ_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_ELEMENT_SZ_MASK) 327 328 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_CH_NUM_MASK (0xC000U) 329 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_CH_NUM_SHIFT (14U) 330 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_CH_NUM_WIDTH (2U) 331 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_CH_NUM(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_CH_NUM_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG1_CH_NUM_MASK) 332 /*! @} */ 333 334 /*! @name MSS_2DCFG2 - DDMA Configuration 2 */ 335 /*! @{ */ 336 337 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG2_TILE_WIDTH_MASK (0xFFFFU) 338 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG2_TILE_WIDTH_SHIFT (0U) 339 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG2_TILE_WIDTH_WIDTH (16U) 340 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG2_TILE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG2_TILE_WIDTH_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG2_TILE_WIDTH_MASK) 341 342 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG2_TILE_HEIGHT_MASK (0xFFFF0000U) 343 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG2_TILE_HEIGHT_SHIFT (16U) 344 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG2_TILE_HEIGHT_WIDTH (16U) 345 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG2_TILE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG2_TILE_HEIGHT_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG2_TILE_HEIGHT_MASK) 346 /*! @} */ 347 348 /*! @name MSS_2DCFG3 - DDMA Configuration 3 */ 349 /*! @{ */ 350 351 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG3_INT_STRIDE_MASK (0xFFFFU) 352 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG3_INT_STRIDE_SHIFT (0U) 353 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG3_INT_STRIDE_WIDTH (16U) 354 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG3_INT_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG3_INT_STRIDE_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG3_INT_STRIDE_MASK) 355 356 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG3_EXT_STRIDE_MASK (0xFFFF0000U) 357 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG3_EXT_STRIDE_SHIFT (16U) 358 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG3_EXT_STRIDE_WIDTH (16U) 359 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG3_EXT_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG3_EXT_STRIDE_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG3_EXT_STRIDE_MASK) 360 /*! @} */ 361 362 /*! @name MSS_2DCFG4 - DDMA Configuration 4 */ 363 /*! @{ */ 364 365 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG4_PADVAL_MASK (0xFFFFFFFFU) 366 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG4_PADVAL_SHIFT (0U) 367 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG4_PADVAL_WIDTH (32U) 368 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG4_PADVAL(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG4_PADVAL_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG4_PADVAL_MASK) 369 /*! @} */ 370 371 /*! @name MSS_2DCFG5 - DDMA Configuration 5 */ 372 /*! @{ */ 373 374 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG5_TCLIP_MASK (0xFFFFU) 375 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG5_TCLIP_SHIFT (0U) 376 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG5_TCLIP_WIDTH (16U) 377 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG5_TCLIP(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG5_TCLIP_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG5_TCLIP_MASK) 378 379 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG5_BCLIP_MASK (0xFFFF0000U) 380 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG5_BCLIP_SHIFT (16U) 381 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG5_BCLIP_WIDTH (16U) 382 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG5_BCLIP(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG5_BCLIP_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG5_BCLIP_MASK) 383 /*! @} */ 384 385 /*! @name MSS_2DCFG6 - DDMA Configuration 6 */ 386 /*! @{ */ 387 388 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG6_LCLIP_MASK (0xFFFFU) 389 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG6_LCLIP_SHIFT (0U) 390 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG6_LCLIP_WIDTH (16U) 391 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG6_LCLIP(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG6_LCLIP_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG6_LCLIP_MASK) 392 393 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG6_RCLIP_MASK (0xFFFF0000U) 394 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG6_RCLIP_SHIFT (16U) 395 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG6_RCLIP_WIDTH (16U) 396 #define DATA_MEMORY_SUBSYSTEM_MSS_2DCFG6_RCLIP(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_2DCFG6_RCLIP_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_2DCFG6_RCLIP_MASK) 397 /*! @} */ 398 399 /*! @name MSS_DDQS - DDMA Status */ 400 /*! @{ */ 401 402 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QEMPTY_MASK (0x1U) 403 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QEMPTY_SHIFT (0U) 404 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QEMPTY_WIDTH (1U) 405 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QEMPTY(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QEMPTY_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QEMPTY_MASK) 406 407 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QFULL_MASK (0x2U) 408 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QFULL_SHIFT (1U) 409 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QFULL_WIDTH (1U) 410 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QFULL(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QFULL_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QFULL_MASK) 411 412 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QCOUNT_MASK (0xCU) 413 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QCOUNT_SHIFT (2U) 414 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QCOUNT_WIDTH (2U) 415 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QCOUNT_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QCOUNT_MASK) 416 417 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QAUTO_MASK (0x40U) 418 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QAUTO_SHIFT (6U) 419 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QAUTO_WIDTH (1U) 420 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QAUTO(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QAUTO_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QAUTO_MASK) 421 422 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QOVFL_MASK (0x80U) 423 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QOVFL_SHIFT (7U) 424 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QOVFL_WIDTH (1U) 425 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QOVFL(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QOVFL_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDQS_QOVFL_MASK) 426 427 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS0_MASK (0x300U) 428 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS0_SHIFT (8U) 429 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS0_WIDTH (2U) 430 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS0(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS0_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS0_MASK) 431 432 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS1_MASK (0xC00U) 433 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS1_SHIFT (10U) 434 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS1_WIDTH (2U) 435 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS1(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS1_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS1_MASK) 436 437 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS2_MASK (0x3000U) 438 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS2_SHIFT (12U) 439 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS2_WIDTH (2U) 440 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS2(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS2_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDQS_STS2_MASK) 441 442 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_LSID_MASK (0x30000U) 443 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_LSID_SHIFT (16U) 444 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_LSID_WIDTH (2U) 445 #define DATA_MEMORY_SUBSYSTEM_MSS_DDQS_LSID(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDQS_LSID_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDQS_LSID_MASK) 446 /*! @} */ 447 448 /*! @name MSS_DDEA - DDMA Address 1 */ 449 /*! @{ */ 450 451 #define DATA_MEMORY_SUBSYSTEM_MSS_DDEA_DDEA_MASK (0xFFFFFFFFU) 452 #define DATA_MEMORY_SUBSYSTEM_MSS_DDEA_DDEA_SHIFT (0U) 453 #define DATA_MEMORY_SUBSYSTEM_MSS_DDEA_DDEA_WIDTH (32U) 454 #define DATA_MEMORY_SUBSYSTEM_MSS_DDEA_DDEA(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDEA_DDEA_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDEA_DDEA_MASK) 455 /*! @} */ 456 457 /*! @name MSS_DDIA - DDMA Address 2 */ 458 /*! @{ */ 459 460 #define DATA_MEMORY_SUBSYSTEM_MSS_DDIA_DDIA_MASK (0xFFFFFFFFU) 461 #define DATA_MEMORY_SUBSYSTEM_MSS_DDIA_DDIA_SHIFT (0U) 462 #define DATA_MEMORY_SUBSYSTEM_MSS_DDIA_DDIA_WIDTH (32U) 463 #define DATA_MEMORY_SUBSYSTEM_MSS_DDIA_DDIA(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDIA_DDIA_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDIA_DDIA_MASK) 464 /*! @} */ 465 466 /*! @name MSS_DDCL - DDMA Control */ 467 /*! @{ */ 468 469 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_IIT_MASK (0x1U) 470 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_IIT_SHIFT (0U) 471 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_IIT_WIDTH (1U) 472 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_IIT(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDCL_IIT_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDCL_IIT_MASK) 473 474 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_TRID_MASK (0xEU) 475 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_TRID_SHIFT (1U) 476 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_TRID_WIDTH (3U) 477 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_TRID(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDCL_TRID_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDCL_TRID_MASK) 478 479 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_BSZ_MASK (0xF0U) 480 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_BSZ_SHIFT (4U) 481 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_BSZ_WIDTH (4U) 482 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_BSZ(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDCL_BSZ_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDCL_BSZ_MASK) 483 484 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDST_MASK (0x100U) 485 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDST_SHIFT (8U) 486 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDST_WIDTH (1U) 487 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDST(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDST_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDST_MASK) 488 489 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_EXTW_MASK (0x200U) 490 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_EXTW_SHIFT (9U) 491 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_EXTW_WIDTH (1U) 492 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_EXTW(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDCL_EXTW_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDCL_EXTW_MASK) 493 494 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDIE_MASK (0x400U) 495 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDIE_SHIFT (10U) 496 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDIE_WIDTH (1U) 497 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDIE(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDIE_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDIE_MASK) 498 499 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_MESSAGE_MASK (0x10000U) 500 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_MESSAGE_SHIFT (16U) 501 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_MESSAGE_WIDTH (1U) 502 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_MESSAGE(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDCL_MESSAGE_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDCL_MESSAGE_MASK) 503 504 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDMA_TASK_ID_MASK (0x7F000000U) 505 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDMA_TASK_ID_SHIFT (24U) 506 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDMA_TASK_ID_WIDTH (7U) 507 #define DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDMA_TASK_ID(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDMA_TASK_ID_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDCL_DDMA_TASK_ID_MASK) 508 /*! @} */ 509 510 /*! @name DDMA_PAUSE - DDMA Pause Control */ 511 /*! @{ */ 512 513 #define DATA_MEMORY_SUBSYSTEM_DDMA_PAUSE_DDMA_PAUSE_MASK (0x1U) 514 #define DATA_MEMORY_SUBSYSTEM_DDMA_PAUSE_DDMA_PAUSE_SHIFT (0U) 515 #define DATA_MEMORY_SUBSYSTEM_DDMA_PAUSE_DDMA_PAUSE_WIDTH (1U) 516 #define DATA_MEMORY_SUBSYSTEM_DDMA_PAUSE_DDMA_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_DDMA_PAUSE_DDMA_PAUSE_SHIFT)) & DATA_MEMORY_SUBSYSTEM_DDMA_PAUSE_DDMA_PAUSE_MASK) 517 518 #define DATA_MEMORY_SUBSYSTEM_DDMA_PAUSE_DDMA_PAUSE_STATUS_MASK (0x2U) 519 #define DATA_MEMORY_SUBSYSTEM_DDMA_PAUSE_DDMA_PAUSE_STATUS_SHIFT (1U) 520 #define DATA_MEMORY_SUBSYSTEM_DDMA_PAUSE_DDMA_PAUSE_STATUS_WIDTH (1U) 521 #define DATA_MEMORY_SUBSYSTEM_DDMA_PAUSE_DDMA_PAUSE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_DDMA_PAUSE_DDMA_PAUSE_STATUS_SHIFT)) & DATA_MEMORY_SUBSYSTEM_DDMA_PAUSE_DDMA_PAUSE_STATUS_MASK) 522 /*! @} */ 523 524 /*! @name MSS_DDESC_ID - DDMA Interrupt Source */ 525 /*! @{ */ 526 527 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q0_TASK_MASK (0x1U) 528 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q0_TASK_SHIFT (0U) 529 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q0_TASK_WIDTH (1U) 530 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q0_TASK(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q0_TASK_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q0_TASK_MASK) 531 532 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q1_TASK_MASK (0x2U) 533 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q1_TASK_SHIFT (1U) 534 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q1_TASK_WIDTH (1U) 535 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q1_TASK(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q1_TASK_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q1_TASK_MASK) 536 537 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q2_TASK_MASK (0x4U) 538 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q2_TASK_SHIFT (2U) 539 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q2_TASK_WIDTH (1U) 540 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q2_TASK(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q2_TASK_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q2_TASK_MASK) 541 542 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q3_TASK_MASK (0x8U) 543 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q3_TASK_SHIFT (3U) 544 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q3_TASK_WIDTH (1U) 545 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q3_TASK(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q3_TASK_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_Q3_TASK_MASK) 546 547 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_MSTR_TASK_MASK (0x10000U) 548 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_MSTR_TASK_SHIFT (16U) 549 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_MSTR_TASK_WIDTH (1U) 550 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_MSTR_TASK(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_MSTR_TASK_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDESC_ID_MSTR_TASK_MASK) 551 /*! @} */ 552 553 /*! @name MSS_DDESC_OV - DDMA Task ID Overwrite Indication */ 554 /*! @{ */ 555 556 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q0_TASK_OV_MASK (0x1U) 557 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q0_TASK_OV_SHIFT (0U) 558 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q0_TASK_OV_WIDTH (1U) 559 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q0_TASK_OV(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q0_TASK_OV_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q0_TASK_OV_MASK) 560 561 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q1_TASK_OV_MASK (0x2U) 562 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q1_TASK_OV_SHIFT (1U) 563 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q1_TASK_OV_WIDTH (1U) 564 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q1_TASK_OV(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q1_TASK_OV_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q1_TASK_OV_MASK) 565 566 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q2_TASK_OV_MASK (0x4U) 567 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q2_TASK_OV_SHIFT (2U) 568 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q2_TASK_OV_WIDTH (1U) 569 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q2_TASK_OV(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q2_TASK_OV_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q2_TASK_OV_MASK) 570 571 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q3_TASK_OV_MASK (0x8U) 572 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q3_TASK_OV_SHIFT (3U) 573 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q3_TASK_OV_WIDTH (1U) 574 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q3_TASK_OV(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q3_TASK_OV_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_Q3_TASK_OV_MASK) 575 576 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_MSTR_TASK_OV_MASK (0x10000U) 577 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_MSTR_TASK_OV_SHIFT (16U) 578 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_MSTR_TASK_OV_WIDTH (1U) 579 #define DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_MSTR_TASK_OV(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_MSTR_TASK_OV_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSS_DDESC_OV_MSTR_TASK_OV_MASK) 580 /*! @} */ 581 582 /*! @name MSTR_TASK_ID - DDMA Task (Master) ID */ 583 /*! @{ */ 584 585 #define DATA_MEMORY_SUBSYSTEM_MSTR_TASK_ID_DDMA_TASK_ID_MASK (0x7FU) 586 #define DATA_MEMORY_SUBSYSTEM_MSTR_TASK_ID_DDMA_TASK_ID_SHIFT (0U) 587 #define DATA_MEMORY_SUBSYSTEM_MSTR_TASK_ID_DDMA_TASK_ID_WIDTH (7U) 588 #define DATA_MEMORY_SUBSYSTEM_MSTR_TASK_ID_DDMA_TASK_ID(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_MSTR_TASK_ID_DDMA_TASK_ID_SHIFT)) & DATA_MEMORY_SUBSYSTEM_MSTR_TASK_ID_DDMA_TASK_ID_MASK) 589 /*! @} */ 590 591 /*! @name QMAN_TASK_IDX - QMAN Task IDx */ 592 /*! @{ */ 593 594 #define DATA_MEMORY_SUBSYSTEM_QMAN_TASK_IDX_DDMA_TASK_ID_MASK (0x7FU) 595 #define DATA_MEMORY_SUBSYSTEM_QMAN_TASK_IDX_DDMA_TASK_ID_SHIFT (0U) 596 #define DATA_MEMORY_SUBSYSTEM_QMAN_TASK_IDX_DDMA_TASK_ID_WIDTH (7U) 597 #define DATA_MEMORY_SUBSYSTEM_QMAN_TASK_IDX_DDMA_TASK_ID(x) (((uint32_t)(((uint32_t)(x)) << DATA_MEMORY_SUBSYSTEM_QMAN_TASK_IDX_DDMA_TASK_ID_SHIFT)) & DATA_MEMORY_SUBSYSTEM_QMAN_TASK_IDX_DDMA_TASK_ID_MASK) 598 /*! @} */ 599 600 /*! 601 * @} 602 */ /* end of group DATA_MEMORY_SUBSYSTEM_Register_Masks */ 603 604 /*! 605 * @} 606 */ /* end of group DATA_MEMORY_SUBSYSTEM_Peripheral_Access_Layer */ 607 608 #endif /* #if !defined(S32Z2_DATA_MEMORY_SUBSYSTEM_H_) */ 609
