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Searched refs:PUF_SRAM_INT_SET_ENABLE_READY_MASK (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h36413 #define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) macro
36416 …2_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h46276 #define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) macro
46279 …2_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h46246 #define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) macro
46249 …2_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h57875 #define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) macro
57878 …2_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK)
DMCXN546_cm33_core1.h57875 #define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) macro
57878 …2_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h57875 #define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) macro
57878 …2_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK)
DMCXN547_cm33_core1.h57875 #define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) macro
57878 …2_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h58610 #define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) macro
58613 …2_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK)
DMCXN947_cm33_core0.h58610 #define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) macro
58613 …2_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h58610 #define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) macro
58613 …2_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK)
DMCXN946_cm33_core1.h58610 #define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) macro
58613 …2_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK)