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Searched refs:PUF_PWRCTRL_RAMINIT_MASK (Results 1 – 1 of 1) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/puf/
Dfsl_puf.c25 #define PUF_PWRCTRL_RAMINIT_MASK (0x8U) macro
85 base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); in puf_powerOn()
86 base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); in puf_powerOn()
116 …base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /*… in PUF_PowerCycle()
119 base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ in PUF_PowerCycle()
120 base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK); /* enable RAM CK */ in PUF_PowerCycle()
121 …base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLAR… in PUF_PowerCycle()
128 base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | in PUF_PowerCycle()
133 base->PWRCTRL = PUF_PWRCTRL_RAMINIT_MASK; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=0 */ in PUF_PowerCycle()
136 base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); in PUF_PowerCycle()
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