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Searched refs:PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h62169 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) macro
62172 …(uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
DMIMXRT1175_cm7.h61267 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) macro
61270 …(uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h60743 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) macro
60746 …(uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
DMIMXRT1165_cm4.h61645 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) macro
61648 …(uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h61267 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) macro
61270 …(uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h65553 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) macro
65556 …(uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
DMIMXRT1166_cm7.h64651 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) macro
64654 …(uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h66074 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) macro
66077 …(uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
DMIMXRT1173_cm7.h65172 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) macro
65175 …(uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h65175 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) macro
65178 …(uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h75842 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) macro
75845 …(uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
DMIMXRT1176_cm4.h76744 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) macro
76747 …(uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)