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Searched refs:PUF_IDXBLK_L_DP_IDX5_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h16589 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
16593 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h16588 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
16592 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core1.h17187 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
17191 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
DLPC55S66_cm33_core0.h17187 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
17191 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h17186 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
17190 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
DLPC55S69_cm33_core0.h17186 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
17190 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h18026 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
18029 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
DMIMXRT685S_cm33.h25823 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
25826 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h25823 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
25826 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h30317 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
30324 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
DMIMXRT595S_cm33.h37583 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
37590 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h35956 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
35963 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h37582 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
37589 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)