Home
last modified time | relevance | path

Searched refs:PUF_IDXBLK_DP_IDXBLK_DP10_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h62118 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) macro
62121 …(((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
DMIMXRT1175_cm7.h61216 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) macro
61219 …(((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h60692 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) macro
60695 …(((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
DMIMXRT1165_cm4.h61594 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) macro
61597 …(((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h61216 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) macro
61219 …(((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h65502 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) macro
65505 …(((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
DMIMXRT1166_cm7.h64600 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) macro
64603 …(((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h66023 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) macro
66026 …(((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
DMIMXRT1173_cm7.h65121 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) macro
65124 …(((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h65124 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) macro
65127 …(((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h75791 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) macro
75794 …(((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
DMIMXRT1176_cm4.h76693 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) macro
76696 …(((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)