1 /* 2 * Copyright 2023-2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef HAL_NXP_DTS_NXP_S32_S32K344_257BGA_PINCTRL_H_ 8 #define HAL_NXP_DTS_NXP_S32_S32K344_257BGA_PINCTRL_H_ 9 10 #include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h> 11 12 /* SIUL */ 13 #define PTA0_EIRQ0 NXP_S32_PINMUX(0, 0, 0, 0, 16, 1) 14 #define PTA1_EIRQ1 NXP_S32_PINMUX(0, 0, 1, 0, 17, 1) 15 #define PTA2_EIRQ2 NXP_S32_PINMUX(0, 0, 2, 0, 18, 1) 16 #define PTA3_EIRQ3 NXP_S32_PINMUX(0, 0, 3, 0, 19, 1) 17 #define PTA4_EIRQ4 NXP_S32_PINMUX(0, 0, 4, 0, 20, 1) 18 #define PTA5_EIRQ5 NXP_S32_PINMUX(0, 0, 5, 0, 21, 1) 19 #define PTA6_EIRQ6 NXP_S32_PINMUX(0, 0, 6, 0, 22, 1) 20 #define PTA7_EIRQ7 NXP_S32_PINMUX(0, 0, 7, 0, 23, 1) 21 #define PTA8_EIRQ16 NXP_S32_PINMUX(0, 0, 8, 0, 32, 1) 22 #define PTA9_EIRQ17 NXP_S32_PINMUX(0, 0, 9, 0, 33, 1) 23 #define PTA10_EIRQ18 NXP_S32_PINMUX(0, 0, 10, 0, 34, 1) 24 #define PTA11_EIRQ19 NXP_S32_PINMUX(0, 0, 11, 0, 35, 1) 25 #define PTA12_EIRQ20 NXP_S32_PINMUX(0, 0, 12, 0, 36, 1) 26 #define PTA13_EIRQ21 NXP_S32_PINMUX(0, 0, 13, 0, 37, 1) 27 #define PTA14_EIRQ22 NXP_S32_PINMUX(0, 0, 14, 0, 38, 1) 28 #define PTA15_EIRQ23 NXP_S32_PINMUX(0, 0, 15, 0, 39, 1) 29 #define PTA16_EIRQ4 NXP_S32_PINMUX(0, 0, 16, 0, 20, 2) 30 #define PTA18_EIRQ0 NXP_S32_PINMUX(0, 0, 18, 0, 16, 2) 31 #define PTA19_EIRQ1 NXP_S32_PINMUX(0, 0, 19, 0, 17, 2) 32 #define PTA20_EIRQ2 NXP_S32_PINMUX(0, 0, 20, 0, 18, 2) 33 #define PTA21_EIRQ3 NXP_S32_PINMUX(0, 0, 21, 0, 19, 2) 34 #define PTA24_GPI24 NXP_S32_PINMUX(0, 0, 23, 0, 24, 0) 35 #define PTA25_GPI25 NXP_S32_PINMUX(0, 0, 23, 0, 25, 0) 36 #define PTA25_EIRQ5 NXP_S32_PINMUX(0, 0, 23, 0, 21, 2) 37 #define PTA28_EIRQ6 NXP_S32_PINMUX(0, 0, 28, 0, 22, 2) 38 #define PTA30_EIRQ7 NXP_S32_PINMUX(0, 0, 30, 0, 23, 2) 39 #define PTB0_EIRQ8 NXP_S32_PINMUX(0, 0, 32, 0, 24, 1) 40 #define PTB1_EIRQ9 NXP_S32_PINMUX(0, 0, 33, 0, 25, 1) 41 #define PTB2_EIRQ10 NXP_S32_PINMUX(0, 0, 34, 0, 26, 1) 42 #define PTB3_EIRQ11 NXP_S32_PINMUX(0, 0, 35, 0, 27, 1) 43 #define PTB4_EIRQ12 NXP_S32_PINMUX(0, 0, 36, 0, 28, 1) 44 #define PTB5_EIRQ13 NXP_S32_PINMUX(0, 0, 37, 0, 29, 1) 45 #define PTB8_EIRQ14 NXP_S32_PINMUX(0, 0, 40, 0, 30, 1) 46 #define PTB9_EIRQ15 NXP_S32_PINMUX(0, 0, 41, 0, 31, 1) 47 #define PTB10_EIRQ24 NXP_S32_PINMUX(0, 0, 42, 0, 40, 1) 48 #define PTB11_EIRQ25 NXP_S32_PINMUX(0, 0, 43, 0, 41, 1) 49 #define PTB12_EIRQ26 NXP_S32_PINMUX(0, 0, 44, 0, 42, 1) 50 #define PTB13_EIRQ27 NXP_S32_PINMUX(0, 0, 45, 0, 43, 1) 51 #define PTB14_EIRQ28 NXP_S32_PINMUX(0, 0, 46, 0, 44, 1) 52 #define PTB15_EIRQ29 NXP_S32_PINMUX(0, 0, 47, 0, 45, 1) 53 #define PTB16_EIRQ30 NXP_S32_PINMUX(0, 0, 48, 0, 46, 1) 54 #define PTB17_EIRQ31 NXP_S32_PINMUX(0, 0, 49, 0, 47, 1) 55 #define PTB21_EIRQ8 NXP_S32_PINMUX(0, 0, 53, 0, 24, 2) 56 #define PTB22_EIRQ9 NXP_S32_PINMUX(0, 0, 54, 0, 25, 2) 57 #define PTB23_EIRQ10 NXP_S32_PINMUX(0, 0, 55, 0, 26, 2) 58 #define PTB24_EIRQ11 NXP_S32_PINMUX(0, 0, 56, 0, 27, 2) 59 #define PTB25_EIRQ12 NXP_S32_PINMUX(0, 0, 57, 0, 28, 2) 60 #define PTB26_EIRQ13 NXP_S32_PINMUX(0, 0, 58, 0, 29, 2) 61 #define PTB28_EIRQ14 NXP_S32_PINMUX(0, 0, 60, 0, 30, 2) 62 #define PTB31_EIRQ15 NXP_S32_PINMUX(0, 0, 63, 0, 31, 2) 63 #define PTC0_EIRQ0 NXP_S32_PINMUX(0, 0, 64, 0, 16, 3) 64 #define PTC1_EIRQ1 NXP_S32_PINMUX(0, 0, 65, 0, 17, 3) 65 #define PTC2_EIRQ2 NXP_S32_PINMUX(0, 0, 66, 0, 18, 3) 66 #define PTC3_EIRQ3 NXP_S32_PINMUX(0, 0, 67, 0, 19, 3) 67 #define PTC4_EIRQ4 NXP_S32_PINMUX(0, 0, 68, 0, 20, 3) 68 #define PTC5_EIRQ5 NXP_S32_PINMUX(0, 0, 69, 0, 21, 3) 69 #define PTC6_EIRQ6 NXP_S32_PINMUX(0, 0, 70, 0, 22, 3) 70 #define PTC7_EIRQ7 NXP_S32_PINMUX(0, 0, 71, 0, 23, 3) 71 #define PTC8_EIRQ16 NXP_S32_PINMUX(0, 0, 72, 0, 32, 2) 72 #define PTC9_EIRQ17 NXP_S32_PINMUX(0, 0, 73, 0, 33, 2) 73 #define PTC10_EIRQ18 NXP_S32_PINMUX(0, 0, 74, 0, 34, 2) 74 #define PTC11_EIRQ19 NXP_S32_PINMUX(0, 0, 75, 0, 35, 2) 75 #define PTC12_EIRQ20 NXP_S32_PINMUX(0, 0, 76, 0, 36, 2) 76 #define PTC13_EIRQ21 NXP_S32_PINMUX(0, 0, 77, 0, 37, 2) 77 #define PTC14_EIRQ22 NXP_S32_PINMUX(0, 0, 78, 0, 38, 2) 78 #define PTC15_EIRQ23 NXP_S32_PINMUX(0, 0, 79, 0, 39, 2) 79 #define PTC20_EIRQ16 NXP_S32_PINMUX(0, 0, 84, 0, 32, 3) 80 #define PTC21_EIRQ17 NXP_S32_PINMUX(0, 0, 85, 0, 33, 3) 81 #define PTC23_EIRQ18 NXP_S32_PINMUX(0, 0, 87, 0, 34, 3) 82 #define PTC24_EIRQ19 NXP_S32_PINMUX(0, 0, 88, 0, 35, 3) 83 #define PTC25_EIRQ20 NXP_S32_PINMUX(0, 0, 89, 0, 36, 3) 84 #define PTC26_EIRQ21 NXP_S32_PINMUX(0, 0, 90, 0, 37, 3) 85 #define PTC27_EIRQ22 NXP_S32_PINMUX(0, 0, 91, 0, 38, 3) 86 #define PTC29_EIRQ23 NXP_S32_PINMUX(0, 0, 93, 0, 39, 3) 87 #define PTD0_EIRQ8 NXP_S32_PINMUX(0, 0, 96, 0, 24, 3) 88 #define PTD1_EIRQ9 NXP_S32_PINMUX(0, 0, 97, 0, 25, 3) 89 #define PTD2_EIRQ10 NXP_S32_PINMUX(0, 0, 98, 0, 26, 3) 90 #define PTD3_EIRQ11 NXP_S32_PINMUX(0, 0, 99, 0, 27, 3) 91 #define PTD4_EIRQ12 NXP_S32_PINMUX(0, 0, 100, 0, 28, 3) 92 #define PTD5_EIRQ13 NXP_S32_PINMUX(0, 0, 101, 0, 29, 3) 93 #define PTD6_EIRQ14 NXP_S32_PINMUX(0, 0, 102, 0, 30, 3) 94 #define PTD7_EIRQ15 NXP_S32_PINMUX(0, 0, 103, 0, 31, 3) 95 #define PTD8_EIRQ24 NXP_S32_PINMUX(0, 0, 104, 0, 40, 2) 96 #define PTD9_EIRQ25 NXP_S32_PINMUX(0, 0, 105, 0, 41, 2) 97 #define PTD10_EIRQ26 NXP_S32_PINMUX(0, 0, 106, 0, 42, 2) 98 #define PTD11_EIRQ27 NXP_S32_PINMUX(0, 0, 107, 0, 43, 2) 99 #define PTD12_EIRQ28 NXP_S32_PINMUX(0, 0, 108, 0, 44, 2) 100 #define PTD13_EIRQ29 NXP_S32_PINMUX(0, 0, 109, 0, 45, 2) 101 #define PTD14_EIRQ30 NXP_S32_PINMUX(0, 0, 110, 0, 46, 3) 102 #define PTD15_EIRQ31 NXP_S32_PINMUX(0, 0, 111, 0, 47, 2) 103 #define PTD17_EIRQ24 NXP_S32_PINMUX(0, 0, 113, 0, 40, 3) 104 #define PTD20_EIRQ25 NXP_S32_PINMUX(0, 0, 116, 0, 41, 3) 105 #define PTD21_EIRQ26 NXP_S32_PINMUX(0, 0, 117, 0, 42, 3) 106 #define PTD22_EIRQ27 NXP_S32_PINMUX(0, 0, 118, 0, 43, 3) 107 #define PTD23_EIRQ28 NXP_S32_PINMUX(0, 0, 119, 0, 44, 3) 108 #define PTD24_EIRQ29 NXP_S32_PINMUX(0, 0, 120, 0, 45, 3) 109 #define PTD27_EIRQ30 NXP_S32_PINMUX(0, 0, 123, 0, 46, 2) 110 #define PTD28_EIRQ31 NXP_S32_PINMUX(0, 0, 124, 0, 47, 3) 111 #define PTE0_EIRQ0 NXP_S32_PINMUX(0, 0, 128, 0, 16, 4) 112 #define PTE1_EIRQ1 NXP_S32_PINMUX(0, 0, 129, 0, 17, 4) 113 #define PTE2_EIRQ2 NXP_S32_PINMUX(0, 0, 130, 0, 18, 4) 114 #define PTE3_EIRQ3 NXP_S32_PINMUX(0, 0, 131, 0, 19, 4) 115 #define PTE4_EIRQ4 NXP_S32_PINMUX(0, 0, 132, 0, 20, 4) 116 #define PTE5_EIRQ5 NXP_S32_PINMUX(0, 0, 133, 0, 21, 4) 117 #define PTE6_EIRQ6 NXP_S32_PINMUX(0, 0, 134, 0, 22, 4) 118 #define PTE8_EIRQ7 NXP_S32_PINMUX(0, 0, 136, 0, 23, 4) 119 #define PTE9_EIRQ8 NXP_S32_PINMUX(0, 0, 137, 0, 24, 4) 120 #define PTE10_EIRQ9 NXP_S32_PINMUX(0, 0, 138, 0, 25, 4) 121 #define PTE11_EIRQ10 NXP_S32_PINMUX(0, 0, 139, 0, 26, 4) 122 #define PTE12_EIRQ11 NXP_S32_PINMUX(0, 0, 140, 0, 27, 4) 123 #define PTE13_EIRQ12 NXP_S32_PINMUX(0, 0, 141, 0, 28, 4) 124 #define PTE14_EIRQ13 NXP_S32_PINMUX(0, 0, 142, 0, 29, 4) 125 #define PTE15_EIRQ14 NXP_S32_PINMUX(0, 0, 143, 0, 30, 4) 126 #define PTE16_EIRQ15 NXP_S32_PINMUX(0, 0, 144, 0, 31, 4) 127 #define PTF0_EIRQ0 NXP_S32_PINMUX(0, 0, 160, 0, 16, 5) 128 #define PTF1_EIRQ1 NXP_S32_PINMUX(0, 0, 161, 0, 17, 5) 129 #define PTF2_EIRQ2 NXP_S32_PINMUX(0, 0, 162, 0, 18, 5) 130 #define PTF3_EIRQ3 NXP_S32_PINMUX(0, 0, 163, 0, 19, 5) 131 #define PTF4_EIRQ4 NXP_S32_PINMUX(0, 0, 164, 0, 20, 5) 132 #define PTF5_EIRQ5 NXP_S32_PINMUX(0, 0, 165, 0, 21, 5) 133 #define PTF6_EIRQ6 NXP_S32_PINMUX(0, 0, 166, 0, 22, 5) 134 #define PTF7_EIRQ7 NXP_S32_PINMUX(0, 0, 167, 0, 23, 5) 135 #define PTF8_EIRQ16 NXP_S32_PINMUX(0, 0, 168, 0, 32, 4) 136 #define PTF9_EIRQ17 NXP_S32_PINMUX(0, 0, 169, 0, 33, 4) 137 #define PTF10_EIRQ18 NXP_S32_PINMUX(0, 0, 170, 0, 34, 4) 138 #define PTF11_EIRQ19 NXP_S32_PINMUX(0, 0, 171, 0, 35, 4) 139 #define PTF12_EIRQ20 NXP_S32_PINMUX(0, 0, 172, 0, 36, 4) 140 #define PTF13_EIRQ21 NXP_S32_PINMUX(0, 0, 173, 0, 37, 4) 141 #define PTF14_EIRQ22 NXP_S32_PINMUX(0, 0, 174, 0, 38, 4) 142 #define PTF15_EIRQ23 NXP_S32_PINMUX(0, 0, 175, 0, 39, 4) 143 #define PTG0_EIRQ8 NXP_S32_PINMUX(0, 0, 192, 0, 24, 5) 144 #define PTG1_EIRQ9 NXP_S32_PINMUX(0, 0, 193, 0, 25, 5) 145 #define PTG2_EIRQ10 NXP_S32_PINMUX(0, 0, 194, 0, 26, 5) 146 #define PTG3_EIRQ11 NXP_S32_PINMUX(0, 0, 195, 0, 27, 5) 147 #define PTG4_EIRQ12 NXP_S32_PINMUX(0, 0, 196, 0, 28, 5) 148 #define PTG5_EIRQ13 NXP_S32_PINMUX(0, 0, 197, 0, 29, 5) 149 #define PTG6_EIRQ14 NXP_S32_PINMUX(0, 0, 198, 0, 30, 5) 150 #define PTG7_EIRQ15 NXP_S32_PINMUX(0, 0, 199, 0, 31, 5) 151 #define PTG8_EIRQ24 NXP_S32_PINMUX(0, 0, 200, 0, 40, 4) 152 #define PTG9_EIRQ25 NXP_S32_PINMUX(0, 0, 201, 0, 41, 4) 153 #define PTG10_EIRQ26 NXP_S32_PINMUX(0, 0, 202, 0, 42, 4) 154 #define PTG11_EIRQ27 NXP_S32_PINMUX(0, 0, 203, 0, 43, 4) 155 #define PTG12_EIRQ28 NXP_S32_PINMUX(0, 0, 204, 0, 44, 4) 156 #define PTG13_EIRQ29 NXP_S32_PINMUX(0, 0, 205, 0, 45, 4) 157 #define PTG14_EIRQ30 NXP_S32_PINMUX(0, 0, 206, 0, 46, 4) 158 #define PTG15_EIRQ31 NXP_S32_PINMUX(0, 0, 207, 0, 47, 4) 159 160 /* LPSPI4 */ 161 #define PTA0_LPSPI4_PCS2_O NXP_S32_PINMUX(0, 0, 0, 1, 0, 0) 162 #define PTA0_LPSPI4_PCS2_I NXP_S32_PINMUX(0, 0, 0, 0, 257, 1) 163 #define PTA1_LPSPI4_PCS1_O NXP_S32_PINMUX(0, 0, 1, 1, 0, 0) 164 #define PTA1_LPSPI4_PCS1_I NXP_S32_PINMUX(0, 0, 1, 0, 256, 1) 165 #define PTA16_LPSPI4_PCS3_O NXP_S32_PINMUX(0, 0, 16, 1, 0, 0) 166 #define PTA16_LPSPI4_PCS3_I NXP_S32_PINMUX(0, 0, 16, 0, 258, 1) 167 #define PTB8_LPSPI4_PCS0_O NXP_S32_PINMUX(0, 0, 40, 1, 0, 0) 168 #define PTB8_LPSPI4_PCS0_I NXP_S32_PINMUX(0, 0, 40, 0, 255, 2) 169 #define PTB9_LPSPI4_SOUT_O NXP_S32_PINMUX(0, 0, 41, 1, 0, 0) 170 #define PTB9_LPSPI4_SOUT_I NXP_S32_PINMUX(0, 0, 41, 0, 261, 2) 171 #define PTB10_LPSPI4_SCK_O NXP_S32_PINMUX(0, 0, 42, 1, 0, 0) 172 #define PTB10_LPSPI4_SCK_I NXP_S32_PINMUX(0, 0, 42, 0, 259, 2) 173 #define PTB11_LPSPI4_SIN_O NXP_S32_PINMUX(0, 0, 43, 1, 0, 0) 174 #define PTB11_LPSPI4_SIN_I NXP_S32_PINMUX(0, 0, 43, 0, 260, 2) 175 #define PTC10_LPSPI4_PCS0_O NXP_S32_PINMUX(0, 0, 74, 5, 0, 0) 176 #define PTC10_LPSPI4_PCS0_I NXP_S32_PINMUX(0, 0, 74, 0, 255, 1) 177 #define PTC11_LPSPI4_SOUT_O NXP_S32_PINMUX(0, 0, 75, 5, 0, 0) 178 #define PTC11_LPSPI4_SOUT_I NXP_S32_PINMUX(0, 0, 75, 0, 261, 1) 179 #define PTC25_LPSPI4_PCS1_O NXP_S32_PINMUX(0, 0, 89, 5, 0, 0) 180 #define PTC25_LPSPI4_PCS1_I NXP_S32_PINMUX(0, 0, 89, 0, 256, 4) 181 #define PTC26_LPSPI4_SIN_O NXP_S32_PINMUX(0, 0, 90, 7, 0, 0) 182 #define PTC26_LPSPI4_SIN_I NXP_S32_PINMUX(0, 0, 90, 0, 260, 1) 183 #define PTC27_LPSPI4_SCK_O NXP_S32_PINMUX(0, 0, 91, 7, 0, 0) 184 #define PTC27_LPSPI4_SCK_I NXP_S32_PINMUX(0, 0, 91, 0, 259, 1) 185 #define PTE21_LPSPI4_SIN_O NXP_S32_PINMUX(0, 0, 149, 6, 0, 0) 186 #define PTE21_LPSPI4_SIN_I NXP_S32_PINMUX(0, 0, 149, 0, 260, 3) 187 #define PTE22_LPSPI4_SCK_O NXP_S32_PINMUX(0, 0, 150, 6, 0, 0) 188 #define PTE22_LPSPI4_SCK_I NXP_S32_PINMUX(0, 0, 150, 0, 259, 3) 189 #define PTE23_LPSPI4_PCS0_O NXP_S32_PINMUX(0, 0, 151, 6, 0, 0) 190 #define PTE23_LPSPI4_PCS0_I NXP_S32_PINMUX(0, 0, 151, 0, 255, 4) 191 #define PTE24_LPSPI4_PCS1_O NXP_S32_PINMUX(0, 0, 152, 6, 0, 0) 192 #define PTE24_LPSPI4_PCS1_I NXP_S32_PINMUX(0, 0, 152, 0, 256, 3) 193 #define PTE25_LPSPI4_SOUT_O NXP_S32_PINMUX(0, 0, 153, 6, 0, 0) 194 #define PTE25_LPSPI4_SOUT_I NXP_S32_PINMUX(0, 0, 153, 0, 261, 3) 195 #define PTF22_LPSPI4_PCS2_O NXP_S32_PINMUX(0, 0, 182, 6, 0, 0) 196 #define PTF22_LPSPI4_PCS2_I NXP_S32_PINMUX(0, 0, 182, 0, 257, 2) 197 #define PTF25_LPSPI4_PCS0_O NXP_S32_PINMUX(0, 0, 185, 6, 0, 0) 198 #define PTF25_LPSPI4_PCS0_I NXP_S32_PINMUX(0, 0, 185, 0, 255, 3) 199 #define PTF26_LPSPI4_PCS1_O NXP_S32_PINMUX(0, 0, 186, 6, 0, 0) 200 #define PTF26_LPSPI4_PCS1_I NXP_S32_PINMUX(0, 0, 186, 0, 256, 2) 201 #define PTF27_LPSPI4_PCS2_O NXP_S32_PINMUX(0, 0, 187, 6, 0, 0) 202 #define PTF27_LPSPI4_PCS2_I NXP_S32_PINMUX(0, 0, 187, 0, 257, 3) 203 #define PTF28_LPSPI4_PCS3_O NXP_S32_PINMUX(0, 0, 188, 6, 0, 0) 204 #define PTF28_LPSPI4_PCS3_I NXP_S32_PINMUX(0, 0, 188, 0, 258, 2) 205 #define PTG12_LPSPI4_PCS3_O NXP_S32_PINMUX(0, 0, 204, 6, 0, 0) 206 #define PTG12_LPSPI4_PCS3_I NXP_S32_PINMUX(0, 0, 204, 0, 258, 3) 207 208 /* EMIOS_0 */ 209 #define PTA0_EMIOS_0_CH17_Y_O NXP_S32_PINMUX(0, 0, 0, 2, 0, 0) 210 #define PTA0_EMIOS_0_CH17_Y_I NXP_S32_PINMUX(0, 0, 0, 0, 65, 2) 211 #define PTA1_EMIOS_0_CH9_H_O NXP_S32_PINMUX(0, 0, 1, 2, 0, 0) 212 #define PTA1_EMIOS_0_CH9_H_I NXP_S32_PINMUX(0, 0, 1, 0, 57, 1) 213 #define PTA10_EMIOS_0_CH12_H_O NXP_S32_PINMUX(0, 0, 10, 2, 0, 0) 214 #define PTA10_EMIOS_0_CH12_H_I NXP_S32_PINMUX(0, 0, 10, 0, 60, 2) 215 #define PTA11_EMIOS_0_CH13_H_O NXP_S32_PINMUX(0, 0, 11, 2, 0, 0) 216 #define PTA11_EMIOS_0_CH13_H_I NXP_S32_PINMUX(0, 0, 11, 0, 61, 1) 217 #define PTA12_EMIOS_0_CH14_H_O NXP_S32_PINMUX(0, 0, 12, 2, 0, 0) 218 #define PTA12_EMIOS_0_CH14_H_I NXP_S32_PINMUX(0, 0, 12, 0, 62, 1) 219 #define PTA13_EMIOS_0_CH15_H_O NXP_S32_PINMUX(0, 0, 13, 2, 0, 0) 220 #define PTA13_EMIOS_0_CH15_H_I NXP_S32_PINMUX(0, 0, 13, 0, 63, 2) 221 #define PTA15_EMIOS_0_CH10_H_O NXP_S32_PINMUX(0, 0, 15, 2, 0, 0) 222 #define PTA15_EMIOS_0_CH10_H_I NXP_S32_PINMUX(0, 0, 15, 0, 58, 2) 223 #define PTA16_EMIOS_0_CH11_H_O NXP_S32_PINMUX(0, 0, 16, 2, 0, 0) 224 #define PTA16_EMIOS_0_CH11_H_I NXP_S32_PINMUX(0, 0, 16, 0, 59, 2) 225 #define PTA17_EMIOS_0_CH6_G_O NXP_S32_PINMUX(0, 0, 17, 2, 0, 0) 226 #define PTA17_EMIOS_0_CH6_G_I NXP_S32_PINMUX(0, 0, 17, 0, 54, 2) 227 #define PTB0_EMIOS_0_CH3_G_O NXP_S32_PINMUX(0, 0, 32, 4, 0, 0) 228 #define PTB0_EMIOS_0_CH3_G_I NXP_S32_PINMUX(0, 0, 32, 0, 51, 4) 229 #define PTB1_EMIOS_0_CH7_G_O NXP_S32_PINMUX(0, 0, 33, 4, 0, 0) 230 #define PTB1_EMIOS_0_CH7_G_I NXP_S32_PINMUX(0, 0, 33, 0, 55, 3) 231 #define PTB2_EMIOS_0_CH8_X_O NXP_S32_PINMUX(0, 0, 34, 2, 0, 0) 232 #define PTB2_EMIOS_0_CH8_X_I NXP_S32_PINMUX(0, 0, 34, 0, 56, 1) 233 #define PTB3_EMIOS_0_CH9_H_O NXP_S32_PINMUX(0, 0, 35, 2, 0, 0) 234 #define PTB3_EMIOS_0_CH9_H_I NXP_S32_PINMUX(0, 0, 35, 0, 57, 2) 235 #define PTB4_EMIOS_0_CH4_G_O NXP_S32_PINMUX(0, 0, 36, 2, 0, 0) 236 #define PTB4_EMIOS_0_CH4_G_I NXP_S32_PINMUX(0, 0, 36, 0, 52, 1) 237 #define PTB5_EMIOS_0_CH5_G_O NXP_S32_PINMUX(0, 0, 37, 2, 0, 0) 238 #define PTB5_EMIOS_0_CH5_G_I NXP_S32_PINMUX(0, 0, 37, 0, 53, 1) 239 #define PTB12_EMIOS_0_CH0_X_O NXP_S32_PINMUX(0, 0, 44, 2, 0, 0) 240 #define PTB12_EMIOS_0_CH0_X_I NXP_S32_PINMUX(0, 0, 44, 0, 48, 1) 241 #define PTB13_EMIOS_0_CH1_G_O NXP_S32_PINMUX(0, 0, 45, 2, 0, 0) 242 #define PTB13_EMIOS_0_CH1_G_I NXP_S32_PINMUX(0, 0, 45, 0, 49, 2) 243 #define PTB14_EMIOS_0_CH2_G_O NXP_S32_PINMUX(0, 0, 46, 2, 0, 0) 244 #define PTB14_EMIOS_0_CH2_G_I NXP_S32_PINMUX(0, 0, 46, 0, 50, 3) 245 #define PTB15_EMIOS_0_CH3_G_O NXP_S32_PINMUX(0, 0, 47, 2, 0, 0) 246 #define PTB15_EMIOS_0_CH3_G_I NXP_S32_PINMUX(0, 0, 47, 0, 51, 1) 247 #define PTB16_EMIOS_0_CH4_G_O NXP_S32_PINMUX(0, 0, 48, 2, 0, 0) 248 #define PTB16_EMIOS_0_CH4_G_I NXP_S32_PINMUX(0, 0, 48, 0, 52, 2) 249 #define PTB17_EMIOS_0_CH5_G_O NXP_S32_PINMUX(0, 0, 49, 2, 0, 0) 250 #define PTB17_EMIOS_0_CH5_G_I NXP_S32_PINMUX(0, 0, 49, 0, 53, 2) 251 #define PTC0_EMIOS_0_CH0_X_O NXP_S32_PINMUX(0, 0, 64, 2, 0, 0) 252 #define PTC0_EMIOS_0_CH14_H_O NXP_S32_PINMUX(0, 0, 64, 6, 0, 0) 253 #define PTC0_EMIOS_0_CH0_X_I NXP_S32_PINMUX(0, 0, 64, 0, 48, 3) 254 #define PTC0_EMIOS_0_CH14_H_I NXP_S32_PINMUX(0, 0, 64, 0, 62, 2) 255 #define PTC1_EMIOS_0_CH1_G_O NXP_S32_PINMUX(0, 0, 65, 2, 0, 0) 256 #define PTC1_EMIOS_0_CH15_H_O NXP_S32_PINMUX(0, 0, 65, 6, 0, 0) 257 #define PTC1_EMIOS_0_CH1_G_I NXP_S32_PINMUX(0, 0, 65, 0, 49, 1) 258 #define PTC1_EMIOS_0_CH15_H_I NXP_S32_PINMUX(0, 0, 65, 0, 63, 1) 259 #define PTC2_EMIOS_0_CH2_G_O NXP_S32_PINMUX(0, 0, 66, 2, 0, 0) 260 #define PTC2_EMIOS_0_CH2_G_I NXP_S32_PINMUX(0, 0, 66, 0, 50, 2) 261 #define PTC3_EMIOS_0_CH3_G_O NXP_S32_PINMUX(0, 0, 67, 2, 0, 0) 262 #define PTC3_EMIOS_0_CH3_G_I NXP_S32_PINMUX(0, 0, 67, 0, 51, 3) 263 #define PTC4_EMIOS_0_CH8_X_O NXP_S32_PINMUX(0, 0, 68, 2, 0, 0) 264 #define PTC4_EMIOS_0_CH8_X_I NXP_S32_PINMUX(0, 0, 68, 0, 56, 2) 265 #define PTC5_EMIOS_0_CH16_X_O NXP_S32_PINMUX(0, 0, 69, 2, 0, 0) 266 #define PTC5_EMIOS_0_CH16_X_I NXP_S32_PINMUX(0, 0, 69, 0, 64, 2) 267 #define PTC10_EMIOS_0_CH6_G_O NXP_S32_PINMUX(0, 0, 74, 1, 0, 0) 268 #define PTC10_EMIOS_0_CH6_G_I NXP_S32_PINMUX(0, 0, 74, 0, 54, 4) 269 #define PTC12_EMIOS_0_CH22_X_O NXP_S32_PINMUX(0, 0, 76, 3, 0, 0) 270 #define PTC12_EMIOS_0_CH22_X_I NXP_S32_PINMUX(0, 0, 76, 0, 70, 2) 271 #define PTC13_EMIOS_0_CH23_X_O NXP_S32_PINMUX(0, 0, 77, 3, 0, 0) 272 #define PTC13_EMIOS_0_CH23_X_I NXP_S32_PINMUX(0, 0, 77, 0, 71, 1) 273 #define PTC14_EMIOS_0_CH10_H_O NXP_S32_PINMUX(0, 0, 78, 2, 0, 0) 274 #define PTC14_EMIOS_0_CH10_H_I NXP_S32_PINMUX(0, 0, 78, 0, 58, 1) 275 #define PTC15_EMIOS_0_CH11_H_O NXP_S32_PINMUX(0, 0, 79, 2, 0, 0) 276 #define PTC15_EMIOS_0_CH11_H_I NXP_S32_PINMUX(0, 0, 79, 0, 59, 1) 277 #define PTC22_EMIOS_0_CH8_X_O NXP_S32_PINMUX(0, 0, 86, 1, 0, 0) 278 #define PTC22_EMIOS_0_CH8_X_I NXP_S32_PINMUX(0, 0, 86, 0, 56, 3) 279 #define PTD0_EMIOS_0_CH2_G_O NXP_S32_PINMUX(0, 0, 96, 2, 0, 0) 280 #define PTD0_EMIOS_0_CH16_X_O NXP_S32_PINMUX(0, 0, 96, 4, 0, 0) 281 #define PTD0_EMIOS_0_CH2_G_I NXP_S32_PINMUX(0, 0, 96, 0, 50, 1) 282 #define PTD0_EMIOS_0_CH16_X_I NXP_S32_PINMUX(0, 0, 96, 0, 64, 1) 283 #define PTD1_EMIOS_0_CH3_G_O NXP_S32_PINMUX(0, 0, 97, 2, 0, 0) 284 #define PTD1_EMIOS_0_CH17_Y_O NXP_S32_PINMUX(0, 0, 97, 4, 0, 0) 285 #define PTD1_EMIOS_0_CH3_G_I NXP_S32_PINMUX(0, 0, 97, 0, 51, 2) 286 #define PTD1_EMIOS_0_CH17_Y_I NXP_S32_PINMUX(0, 0, 97, 0, 65, 1) 287 #define PTD5_EMIOS_0_CH19_Y_O NXP_S32_PINMUX(0, 0, 101, 2, 0, 0) 288 #define PTD5_EMIOS_0_CH2_G_O NXP_S32_PINMUX(0, 0, 101, 3, 0, 0) 289 #define PTD5_EMIOS_0_CH2_G_I NXP_S32_PINMUX(0, 0, 101, 0, 50, 4) 290 #define PTD5_EMIOS_0_CH19_Y_I NXP_S32_PINMUX(0, 0, 101, 0, 67, 2) 291 #define PTD8_EMIOS_0_CH12_H_O NXP_S32_PINMUX(0, 0, 104, 6, 0, 0) 292 #define PTD8_EMIOS_0_CH12_H_I NXP_S32_PINMUX(0, 0, 104, 0, 60, 1) 293 #define PTD9_EMIOS_0_CH13_H_O NXP_S32_PINMUX(0, 0, 105, 6, 0, 0) 294 #define PTD9_EMIOS_0_CH13_H_I NXP_S32_PINMUX(0, 0, 105, 0, 61, 2) 295 #define PTD10_EMIOS_0_CH16_X_O NXP_S32_PINMUX(0, 0, 106, 2, 0, 0) 296 #define PTD10_EMIOS_0_CH16_X_I NXP_S32_PINMUX(0, 0, 106, 0, 64, 3) 297 #define PTD11_EMIOS_0_CH17_Y_O NXP_S32_PINMUX(0, 0, 107, 2, 0, 0) 298 #define PTD11_EMIOS_0_CH17_Y_I NXP_S32_PINMUX(0, 0, 107, 0, 65, 3) 299 #define PTD12_EMIOS_0_CH18_Y_O NXP_S32_PINMUX(0, 0, 108, 2, 0, 0) 300 #define PTD12_EMIOS_0_CH18_Y_I NXP_S32_PINMUX(0, 0, 108, 0, 66, 1) 301 #define PTD13_EMIOS_0_CH20_Y_O NXP_S32_PINMUX(0, 0, 109, 2, 0, 0) 302 #define PTD13_EMIOS_0_CH20_Y_I NXP_S32_PINMUX(0, 0, 109, 0, 68, 1) 303 #define PTD14_EMIOS_0_CH21_Y_O NXP_S32_PINMUX(0, 0, 110, 2, 0, 0) 304 #define PTD14_EMIOS_0_CH21_Y_I NXP_S32_PINMUX(0, 0, 110, 0, 69, 1) 305 #define PTD15_EMIOS_0_CH0_X_O NXP_S32_PINMUX(0, 0, 111, 2, 0, 0) 306 #define PTD15_EMIOS_0_CH0_X_I NXP_S32_PINMUX(0, 0, 111, 0, 48, 2) 307 #define PTD16_EMIOS_0_CH1_G_O NXP_S32_PINMUX(0, 0, 112, 2, 0, 0) 308 #define PTD16_EMIOS_0_CH1_G_I NXP_S32_PINMUX(0, 0, 112, 0, 49, 3) 309 #define PTD17_EMIOS_0_CH18_Y_O NXP_S32_PINMUX(0, 0, 113, 2, 0, 0) 310 #define PTD17_EMIOS_0_CH18_Y_I NXP_S32_PINMUX(0, 0, 113, 0, 66, 3) 311 #define PTE2_EMIOS_0_CH3_G_O NXP_S32_PINMUX(0, 0, 130, 3, 0, 0) 312 #define PTE2_EMIOS_0_CH3_G_I NXP_S32_PINMUX(0, 0, 130, 0, 51, 5) 313 #define PTE3_EMIOS_0_CH19_Y_O NXP_S32_PINMUX(0, 0, 131, 3, 0, 0) 314 #define PTE3_EMIOS_0_CH19_Y_I NXP_S32_PINMUX(0, 0, 131, 0, 67, 4) 315 #define PTE4_EMIOS_0_CH18_Y_O NXP_S32_PINMUX(0, 0, 132, 4, 0, 0) 316 #define PTE4_EMIOS_0_CH18_Y_I NXP_S32_PINMUX(0, 0, 132, 0, 66, 2) 317 #define PTE5_EMIOS_0_CH19_Y_O NXP_S32_PINMUX(0, 0, 133, 4, 0, 0) 318 #define PTE5_EMIOS_0_CH19_Y_I NXP_S32_PINMUX(0, 0, 133, 0, 67, 1) 319 #define PTE7_EMIOS_0_CH7_G_O NXP_S32_PINMUX(0, 0, 135, 2, 0, 0) 320 #define PTE7_EMIOS_0_CH7_G_I NXP_S32_PINMUX(0, 0, 135, 0, 55, 2) 321 #define PTE8_EMIOS_0_CH6_G_O NXP_S32_PINMUX(0, 0, 136, 2, 0, 0) 322 #define PTE8_EMIOS_0_CH6_G_I NXP_S32_PINMUX(0, 0, 136, 0, 54, 1) 323 #define PTE9_EMIOS_0_CH7_G_O NXP_S32_PINMUX(0, 0, 137, 2, 0, 0) 324 #define PTE9_EMIOS_0_CH7_G_I NXP_S32_PINMUX(0, 0, 137, 0, 55, 1) 325 #define PTE10_EMIOS_0_CH20_Y_O NXP_S32_PINMUX(0, 0, 138, 4, 0, 0) 326 #define PTE10_EMIOS_0_CH20_Y_I NXP_S32_PINMUX(0, 0, 138, 0, 68, 2) 327 #define PTE11_EMIOS_0_CH1_G_O NXP_S32_PINMUX(0, 0, 139, 3, 0, 0) 328 #define PTE11_EMIOS_0_CH21_Y_O NXP_S32_PINMUX(0, 0, 139, 4, 0, 0) 329 #define PTE11_EMIOS_0_CH1_G_I NXP_S32_PINMUX(0, 0, 139, 0, 49, 4) 330 #define PTE11_EMIOS_0_CH21_Y_I NXP_S32_PINMUX(0, 0, 139, 0, 69, 2) 331 #define PTE14_EMIOS_0_CH19_Y_O NXP_S32_PINMUX(0, 0, 142, 1, 0, 0) 332 #define PTE14_EMIOS_0_CH19_Y_I NXP_S32_PINMUX(0, 0, 142, 0, 67, 3) 333 #define PTE15_EMIOS_0_CH22_X_O NXP_S32_PINMUX(0, 0, 143, 4, 0, 0) 334 #define PTE15_EMIOS_0_CH22_X_I NXP_S32_PINMUX(0, 0, 143, 0, 70, 1) 335 #define PTE16_EMIOS_0_CH23_X_O NXP_S32_PINMUX(0, 0, 144, 4, 0, 0) 336 #define PTE16_EMIOS_0_CH23_X_I NXP_S32_PINMUX(0, 0, 144, 0, 71, 2) 337 #define PTE19_EMIOS_0_CH22_X_O NXP_S32_PINMUX(0, 0, 147, 2, 0, 0) 338 #define PTE19_EMIOS_0_CH22_X_I NXP_S32_PINMUX(0, 0, 147, 0, 70, 3) 339 340 /* LCU0 */ 341 #define PTA0_LCU0_OUT4 NXP_S32_PINMUX(0, 0, 0, 3, 0, 0) 342 #define PTA1_LCU0_OUT5 NXP_S32_PINMUX(0, 0, 1, 5, 0, 0) 343 #define PTA2_LCU0_OUT3 NXP_S32_PINMUX(0, 0, 2, 6, 0, 0) 344 #define PTA3_LCU0_OUT2 NXP_S32_PINMUX(0, 0, 3, 4, 0, 0) 345 #define PTB8_LCU0_OUT11 NXP_S32_PINMUX(0, 0, 40, 5, 0, 0) 346 #define PTB9_LCU0_OUT10 NXP_S32_PINMUX(0, 0, 41, 6, 0, 0) 347 #define PTB10_LCU0_OUT9 NXP_S32_PINMUX(0, 0, 42, 6, 0, 0) 348 #define PTB11_LCU0_OUT8 NXP_S32_PINMUX(0, 0, 43, 5, 0, 0) 349 #define PTB12_LCU0_OUT2 NXP_S32_PINMUX(0, 0, 44, 6, 0, 0) 350 #define PTB13_LCU0_OUT3 NXP_S32_PINMUX(0, 0, 45, 5, 0, 0) 351 #define PTB14_LCU0_OUT7 NXP_S32_PINMUX(0, 0, 46, 4, 0, 0) 352 #define PTC6_LCU0_OUT7 NXP_S32_PINMUX(0, 0, 70, 4, 0, 0) 353 #define PTC7_LCU0_OUT6 NXP_S32_PINMUX(0, 0, 71, 4, 0, 0) 354 #define PTD2_LCU0_OUT1 NXP_S32_PINMUX(0, 0, 98, 1, 0, 0) 355 #define PTD3_LCU0_OUT0 NXP_S32_PINMUX(0, 0, 99, 6, 0, 0) 356 #define PTD4_LCU0_OUT6 NXP_S32_PINMUX(0, 0, 100, 5, 0, 0) 357 #define PTD21_LCU0_OUT4 NXP_S32_PINMUX(0, 0, 117, 5, 0, 0) 358 #define PTD22_LCU0_OUT5 NXP_S32_PINMUX(0, 0, 118, 6, 0, 0) 359 #define PTD23_LCU0_OUT10 NXP_S32_PINMUX(0, 0, 119, 6, 0, 0) 360 #define PTD24_LCU0_OUT11 NXP_S32_PINMUX(0, 0, 120, 6, 0, 0) 361 #define PTD26_LCU0_OUT0 NXP_S32_PINMUX(0, 0, 122, 7, 0, 0) 362 #define PTD27_LCU0_OUT1 NXP_S32_PINMUX(0, 0, 123, 7, 0, 0) 363 #define PTD28_LCU0_OUT2 NXP_S32_PINMUX(0, 0, 124, 5, 0, 0) 364 #define PTD29_LCU0_OUT3 NXP_S32_PINMUX(0, 0, 125, 5, 0, 0) 365 #define PTD30_LCU0_OUT8 NXP_S32_PINMUX(0, 0, 126, 5, 0, 0) 366 #define PTD31_LCU0_OUT9 NXP_S32_PINMUX(0, 0, 127, 5, 0, 0) 367 368 /* FXIO */ 369 #define PTA0_FXIO_D2_O NXP_S32_PINMUX(0, 0, 0, 4, 0, 0) 370 #define PTA0_FXIO_D2_I NXP_S32_PINMUX(0, 0, 0, 0, 154, 2) 371 #define PTA1_FXIO_D3_O NXP_S32_PINMUX(0, 0, 1, 4, 0, 0) 372 #define PTA1_FXIO_D3_I NXP_S32_PINMUX(0, 0, 1, 0, 155, 1) 373 #define PTA2_FXIO_D4_O NXP_S32_PINMUX(0, 0, 2, 5, 0, 0) 374 #define PTA2_FXIO_D4_I NXP_S32_PINMUX(0, 0, 2, 0, 156, 3) 375 #define PTA3_FXIO_D5_O NXP_S32_PINMUX(0, 0, 3, 5, 0, 0) 376 #define PTA3_FXIO_D5_I NXP_S32_PINMUX(0, 0, 3, 0, 157, 3) 377 #define PTA4_FXIO_D6_O NXP_S32_PINMUX(0, 0, 4, 3, 0, 0) 378 #define PTA4_FXIO_D6_I NXP_S32_PINMUX(0, 0, 4, 0, 158, 8) 379 #define PTA6_FXIO_D19_O NXP_S32_PINMUX(0, 0, 6, 5, 0, 0) 380 #define PTA6_FXIO_D19_I NXP_S32_PINMUX(0, 0, 6, 0, 171, 4) 381 #define PTA7_FXIO_D9_O NXP_S32_PINMUX(0, 0, 7, 6, 0, 0) 382 #define PTA7_FXIO_D9_I NXP_S32_PINMUX(0, 0, 7, 0, 161, 3) 383 #define PTA8_FXIO_D6_O NXP_S32_PINMUX(0, 0, 8, 4, 0, 0) 384 #define PTA8_FXIO_D6_I NXP_S32_PINMUX(0, 0, 8, 0, 158, 2) 385 #define PTA9_FXIO_D7_O NXP_S32_PINMUX(0, 0, 9, 4, 0, 0) 386 #define PTA9_FXIO_D7_I NXP_S32_PINMUX(0, 0, 9, 0, 159, 2) 387 #define PTA10_FXIO_D0_O NXP_S32_PINMUX(0, 0, 10, 4, 0, 0) 388 #define PTA10_FXIO_D0_I NXP_S32_PINMUX(0, 0, 10, 0, 152, 2) 389 #define PTA11_FXIO_D1_O NXP_S32_PINMUX(0, 0, 11, 4, 0, 0) 390 #define PTA11_FXIO_D1_I NXP_S32_PINMUX(0, 0, 11, 0, 153, 2) 391 #define PTA12_FXIO_D9_O NXP_S32_PINMUX(0, 0, 12, 5, 0, 0) 392 #define PTA12_FXIO_D9_I NXP_S32_PINMUX(0, 0, 12, 0, 161, 4) 393 #define PTA13_FXIO_D8_O NXP_S32_PINMUX(0, 0, 13, 5, 0, 0) 394 #define PTA13_FXIO_D8_I NXP_S32_PINMUX(0, 0, 13, 0, 160, 4) 395 #define PTA14_FXIO_D14_O NXP_S32_PINMUX(0, 0, 14, 6, 0, 0) 396 #define PTA14_FXIO_D14_I NXP_S32_PINMUX(0, 0, 14, 0, 166, 4) 397 #define PTA15_FXIO_D31_O NXP_S32_PINMUX(0, 0, 15, 7, 0, 0) 398 #define PTA15_FXIO_D31_I NXP_S32_PINMUX(0, 0, 15, 0, 183, 1) 399 #define PTA16_FXIO_D30_O NXP_S32_PINMUX(0, 0, 16, 7, 0, 0) 400 #define PTA16_FXIO_D30_I NXP_S32_PINMUX(0, 0, 16, 0, 182, 1) 401 #define PTA17_FXIO_D19_O NXP_S32_PINMUX(0, 0, 17, 7, 0, 0) 402 #define PTA17_FXIO_D19_I NXP_S32_PINMUX(0, 0, 17, 0, 171, 1) 403 #define PTA21_FXIO_D0_O NXP_S32_PINMUX(0, 0, 21, 3, 0, 0) 404 #define PTA21_FXIO_D0_I NXP_S32_PINMUX(0, 0, 21, 0, 152, 3) 405 #define PTA22_FXIO_D1_O NXP_S32_PINMUX(0, 0, 22, 3, 0, 0) 406 #define PTA22_FXIO_D1_I NXP_S32_PINMUX(0, 0, 22, 0, 153, 3) 407 #define PTA23_FXIO_D2_O NXP_S32_PINMUX(0, 0, 23, 3, 0, 0) 408 #define PTA23_FXIO_D2_I NXP_S32_PINMUX(0, 0, 23, 0, 154, 3) 409 #define PTA24_FXIO_D3 NXP_S32_PINMUX(0, 0, 23, 0, 155, 3) 410 #define PTA25_FXIO_D2 NXP_S32_PINMUX(0, 0, 23, 0, 154, 6) 411 #define PTA26_FXIO_D1_O NXP_S32_PINMUX(0, 0, 26, 5, 0, 0) 412 #define PTA26_FXIO_D1_I NXP_S32_PINMUX(0, 0, 26, 0, 153, 7) 413 #define PTA27_FXIO_D5_O NXP_S32_PINMUX(0, 0, 27, 1, 0, 0) 414 #define PTA27_FXIO_D5_I NXP_S32_PINMUX(0, 0, 27, 0, 157, 9) 415 #define PTA31_FXIO_D0_O NXP_S32_PINMUX(0, 0, 31, 3, 0, 0) 416 #define PTA31_FXIO_D0_I NXP_S32_PINMUX(0, 0, 31, 0, 152, 6) 417 #define PTB0_FXIO_D14_O NXP_S32_PINMUX(0, 0, 32, 2, 0, 0) 418 #define PTB0_FXIO_D14_I NXP_S32_PINMUX(0, 0, 32, 0, 166, 3) 419 #define PTB2_FXIO_D18_O NXP_S32_PINMUX(0, 0, 34, 7, 0, 0) 420 #define PTB2_FXIO_D18_I NXP_S32_PINMUX(0, 0, 34, 0, 170, 1) 421 #define PTB3_FXIO_D17_O NXP_S32_PINMUX(0, 0, 35, 7, 0, 0) 422 #define PTB3_FXIO_D17_I NXP_S32_PINMUX(0, 0, 35, 0, 169, 1) 423 #define PTB8_FXIO_D29_O NXP_S32_PINMUX(0, 0, 40, 7, 0, 0) 424 #define PTB8_FXIO_D29_I NXP_S32_PINMUX(0, 0, 40, 0, 181, 1) 425 #define PTB9_FXIO_D28_O NXP_S32_PINMUX(0, 0, 41, 7, 0, 0) 426 #define PTB9_FXIO_D28_I NXP_S32_PINMUX(0, 0, 41, 0, 180, 1) 427 #define PTB10_FXIO_D27_O NXP_S32_PINMUX(0, 0, 42, 7, 0, 0) 428 #define PTB10_FXIO_D27_I NXP_S32_PINMUX(0, 0, 42, 0, 179, 1) 429 #define PTB11_FXIO_D26_O NXP_S32_PINMUX(0, 0, 43, 7, 0, 0) 430 #define PTB11_FXIO_D26_I NXP_S32_PINMUX(0, 0, 43, 0, 178, 1) 431 #define PTB12_FXIO_D25_O NXP_S32_PINMUX(0, 0, 44, 7, 0, 0) 432 #define PTB12_FXIO_D25_I NXP_S32_PINMUX(0, 0, 44, 0, 177, 1) 433 #define PTB13_FXIO_D8_O NXP_S32_PINMUX(0, 0, 45, 3, 0, 0) 434 #define PTB13_FXIO_D24_O NXP_S32_PINMUX(0, 0, 45, 7, 0, 0) 435 #define PTB13_FXIO_D8_I NXP_S32_PINMUX(0, 0, 45, 0, 160, 3) 436 #define PTB13_FXIO_D24_I NXP_S32_PINMUX(0, 0, 45, 0, 176, 1) 437 #define PTB14_FXIO_D23_O NXP_S32_PINMUX(0, 0, 46, 7, 0, 0) 438 #define PTB14_FXIO_D23_I NXP_S32_PINMUX(0, 0, 46, 0, 175, 1) 439 #define PTB15_FXIO_D22_O NXP_S32_PINMUX(0, 0, 47, 7, 0, 0) 440 #define PTB15_FXIO_D22_I NXP_S32_PINMUX(0, 0, 47, 0, 174, 1) 441 #define PTB16_FXIO_D21_O NXP_S32_PINMUX(0, 0, 48, 7, 0, 0) 442 #define PTB16_FXIO_D21_I NXP_S32_PINMUX(0, 0, 48, 0, 173, 1) 443 #define PTB17_FXIO_D20_O NXP_S32_PINMUX(0, 0, 49, 7, 0, 0) 444 #define PTB17_FXIO_D20_I NXP_S32_PINMUX(0, 0, 49, 0, 172, 1) 445 #define PTB18_FXIO_D1_O NXP_S32_PINMUX(0, 0, 50, 3, 0, 0) 446 #define PTB18_FXIO_D1_I NXP_S32_PINMUX(0, 0, 50, 0, 153, 6) 447 #define PTB19_FXIO_D2_O NXP_S32_PINMUX(0, 0, 51, 3, 0, 0) 448 #define PTB19_FXIO_D2_I NXP_S32_PINMUX(0, 0, 51, 0, 154, 5) 449 #define PTB20_FXIO_D3_O NXP_S32_PINMUX(0, 0, 52, 3, 0, 0) 450 #define PTB20_FXIO_D3_I NXP_S32_PINMUX(0, 0, 52, 0, 155, 5) 451 #define PTB21_FXIO_D4_O NXP_S32_PINMUX(0, 0, 53, 3, 0, 0) 452 #define PTB21_FXIO_D4_I NXP_S32_PINMUX(0, 0, 53, 0, 156, 5) 453 #define PTB22_FXIO_D15_O NXP_S32_PINMUX(0, 0, 54, 6, 0, 0) 454 #define PTB22_FXIO_D15_I NXP_S32_PINMUX(0, 0, 54, 0, 167, 5) 455 #define PTB23_FXIO_D4_O NXP_S32_PINMUX(0, 0, 55, 3, 0, 0) 456 #define PTB23_FXIO_D4_I NXP_S32_PINMUX(0, 0, 55, 0, 156, 6) 457 #define PTB24_FXIO_D5_O NXP_S32_PINMUX(0, 0, 56, 3, 0, 0) 458 #define PTB24_FXIO_D5_I NXP_S32_PINMUX(0, 0, 56, 0, 157, 6) 459 #define PTB25_FXIO_D6_O NXP_S32_PINMUX(0, 0, 57, 3, 0, 0) 460 #define PTB25_FXIO_D6_I NXP_S32_PINMUX(0, 0, 57, 0, 158, 5) 461 #define PTB26_FXIO_D7_O NXP_S32_PINMUX(0, 0, 58, 3, 0, 0) 462 #define PTB26_FXIO_D7_I NXP_S32_PINMUX(0, 0, 58, 0, 159, 6) 463 #define PTB27_FXIO_D8_O NXP_S32_PINMUX(0, 0, 59, 3, 0, 0) 464 #define PTB27_FXIO_D8_I NXP_S32_PINMUX(0, 0, 59, 0, 160, 2) 465 #define PTB28_FXIO_D9_O NXP_S32_PINMUX(0, 0, 60, 3, 0, 0) 466 #define PTB28_FXIO_D9_I NXP_S32_PINMUX(0, 0, 60, 0, 161, 2) 467 #define PTB29_FXIO_D10_O NXP_S32_PINMUX(0, 0, 61, 3, 0, 0) 468 #define PTB29_FXIO_D10_I NXP_S32_PINMUX(0, 0, 61, 0, 162, 2) 469 #define PTB30_FXIO_D11_O NXP_S32_PINMUX(0, 0, 62, 3, 0, 0) 470 #define PTB30_FXIO_D11_I NXP_S32_PINMUX(0, 0, 62, 0, 163, 2) 471 #define PTC1_FXIO_D5_O NXP_S32_PINMUX(0, 0, 65, 4, 0, 0) 472 #define PTC1_FXIO_D5_I NXP_S32_PINMUX(0, 0, 65, 0, 157, 7) 473 #define PTC4_FXIO_D5_O NXP_S32_PINMUX(0, 0, 68, 4, 0, 0) 474 #define PTC4_FXIO_D5_I NXP_S32_PINMUX(0, 0, 68, 0, 157, 8) 475 #define PTC5_FXIO_D4_O NXP_S32_PINMUX(0, 0, 69, 4, 0, 0) 476 #define PTC5_FXIO_D4_I NXP_S32_PINMUX(0, 0, 69, 0, 156, 7) 477 #define PTC6_FXIO_D11_O NXP_S32_PINMUX(0, 0, 70, 2, 0, 0) 478 #define PTC6_FXIO_D11_I NXP_S32_PINMUX(0, 0, 70, 0, 163, 3) 479 #define PTC7_FXIO_D10_O NXP_S32_PINMUX(0, 0, 71, 1, 0, 0) 480 #define PTC7_FXIO_D10_I NXP_S32_PINMUX(0, 0, 71, 0, 162, 3) 481 #define PTC8_FXIO_D12_O NXP_S32_PINMUX(0, 0, 72, 7, 0, 0) 482 #define PTC8_FXIO_D12_I NXP_S32_PINMUX(0, 0, 72, 0, 164, 3) 483 #define PTC9_FXIO_D13_O NXP_S32_PINMUX(0, 0, 73, 7, 0, 0) 484 #define PTC9_FXIO_D13_I NXP_S32_PINMUX(0, 0, 73, 0, 165, 3) 485 #define PTC11_FXIO_D15_O NXP_S32_PINMUX(0, 0, 75, 4, 0, 0) 486 #define PTC11_FXIO_D19_O NXP_S32_PINMUX(0, 0, 75, 6, 0, 0) 487 #define PTC11_FXIO_D15_I NXP_S32_PINMUX(0, 0, 75, 0, 167, 3) 488 #define PTC11_FXIO_D19_I NXP_S32_PINMUX(0, 0, 75, 0, 171, 3) 489 #define PTC12_FXIO_D19_O NXP_S32_PINMUX(0, 0, 76, 5, 0, 0) 490 #define PTC12_FXIO_D19_I NXP_S32_PINMUX(0, 0, 76, 0, 171, 5) 491 #define PTC13_FXIO_D16_O NXP_S32_PINMUX(0, 0, 77, 5, 0, 0) 492 #define PTC13_FXIO_D16_I NXP_S32_PINMUX(0, 0, 77, 0, 168, 3) 493 #define PTC14_FXIO_D16_O NXP_S32_PINMUX(0, 0, 78, 7, 0, 0) 494 #define PTC14_FXIO_D16_I NXP_S32_PINMUX(0, 0, 78, 0, 168, 1) 495 #define PTC16_FXIO_D15_O NXP_S32_PINMUX(0, 0, 80, 6, 0, 0) 496 #define PTC16_FXIO_D15_I NXP_S32_PINMUX(0, 0, 80, 0, 167, 1) 497 #define PTC17_FXIO_D14_O NXP_S32_PINMUX(0, 0, 81, 6, 0, 0) 498 #define PTC17_FXIO_D14_I NXP_S32_PINMUX(0, 0, 81, 0, 166, 1) 499 #define PTC18_FXIO_D6_O NXP_S32_PINMUX(0, 0, 82, 2, 0, 0) 500 #define PTC18_FXIO_D12_O NXP_S32_PINMUX(0, 0, 82, 3, 0, 0) 501 #define PTC18_FXIO_D6_I NXP_S32_PINMUX(0, 0, 82, 0, 158, 9) 502 #define PTC18_FXIO_D12_I NXP_S32_PINMUX(0, 0, 82, 0, 164, 2) 503 #define PTC19_FXIO_D13_O NXP_S32_PINMUX(0, 0, 83, 3, 0, 0) 504 #define PTC19_FXIO_D13_I NXP_S32_PINMUX(0, 0, 83, 0, 165, 2) 505 #define PTC20_FXIO_D14_O NXP_S32_PINMUX(0, 0, 84, 3, 0, 0) 506 #define PTC20_FXIO_D14_I NXP_S32_PINMUX(0, 0, 84, 0, 166, 2) 507 #define PTC21_FXIO_D15_O NXP_S32_PINMUX(0, 0, 85, 3, 0, 0) 508 #define PTC21_FXIO_D15_I NXP_S32_PINMUX(0, 0, 85, 0, 167, 2) 509 #define PTC23_FXIO_D16_O NXP_S32_PINMUX(0, 0, 87, 3, 0, 0) 510 #define PTC23_FXIO_D16_I NXP_S32_PINMUX(0, 0, 87, 0, 168, 2) 511 #define PTC24_FXIO_D17_O NXP_S32_PINMUX(0, 0, 88, 3, 0, 0) 512 #define PTC24_FXIO_D17_I NXP_S32_PINMUX(0, 0, 88, 0, 169, 2) 513 #define PTC25_FXIO_D18_O NXP_S32_PINMUX(0, 0, 89, 3, 0, 0) 514 #define PTC25_FXIO_D18_I NXP_S32_PINMUX(0, 0, 89, 0, 170, 2) 515 #define PTC26_FXIO_D19_O NXP_S32_PINMUX(0, 0, 90, 3, 0, 0) 516 #define PTC26_FXIO_D19_I NXP_S32_PINMUX(0, 0, 90, 0, 171, 2) 517 #define PTC27_FXIO_D20_O NXP_S32_PINMUX(0, 0, 91, 3, 0, 0) 518 #define PTC27_FXIO_D20_I NXP_S32_PINMUX(0, 0, 91, 0, 172, 2) 519 #define PTC28_FXIO_D21_O NXP_S32_PINMUX(0, 0, 92, 3, 0, 0) 520 #define PTC28_FXIO_D2_O NXP_S32_PINMUX(0, 0, 92, 4, 0, 0) 521 #define PTC28_FXIO_D2_I NXP_S32_PINMUX(0, 0, 92, 0, 154, 7) 522 #define PTC28_FXIO_D21_I NXP_S32_PINMUX(0, 0, 92, 0, 173, 2) 523 #define PTC29_FXIO_D22_O NXP_S32_PINMUX(0, 0, 93, 3, 0, 0) 524 #define PTC29_FXIO_D3_O NXP_S32_PINMUX(0, 0, 93, 7, 0, 0) 525 #define PTC29_FXIO_D3_I NXP_S32_PINMUX(0, 0, 93, 0, 155, 6) 526 #define PTC29_FXIO_D22_I NXP_S32_PINMUX(0, 0, 93, 0, 174, 2) 527 #define PTC30_FXIO_D0_O NXP_S32_PINMUX(0, 0, 94, 3, 0, 0) 528 #define PTC30_FXIO_D23_O NXP_S32_PINMUX(0, 0, 94, 7, 0, 0) 529 #define PTC30_FXIO_D0_I NXP_S32_PINMUX(0, 0, 94, 0, 152, 4) 530 #define PTC30_FXIO_D23_I NXP_S32_PINMUX(0, 0, 94, 0, 175, 2) 531 #define PTC31_FXIO_D1_O NXP_S32_PINMUX(0, 0, 95, 3, 0, 0) 532 #define PTC31_FXIO_D24_O NXP_S32_PINMUX(0, 0, 95, 7, 0, 0) 533 #define PTC31_FXIO_D1_I NXP_S32_PINMUX(0, 0, 95, 0, 153, 4) 534 #define PTC31_FXIO_D24_I NXP_S32_PINMUX(0, 0, 95, 0, 176, 2) 535 #define PTD0_FXIO_D0_O NXP_S32_PINMUX(0, 0, 96, 6, 0, 0) 536 #define PTD0_FXIO_D0_I NXP_S32_PINMUX(0, 0, 96, 0, 152, 1) 537 #define PTD1_FXIO_D1_O NXP_S32_PINMUX(0, 0, 97, 6, 0, 0) 538 #define PTD1_FXIO_D1_I NXP_S32_PINMUX(0, 0, 97, 0, 153, 1) 539 #define PTD2_FXIO_D4_O NXP_S32_PINMUX(0, 0, 98, 4, 0, 0) 540 #define PTD2_FXIO_D6_O NXP_S32_PINMUX(0, 0, 98, 5, 0, 0) 541 #define PTD2_FXIO_D4_I NXP_S32_PINMUX(0, 0, 98, 0, 156, 1) 542 #define PTD2_FXIO_D6_I NXP_S32_PINMUX(0, 0, 98, 0, 158, 3) 543 #define PTD3_FXIO_D5_O NXP_S32_PINMUX(0, 0, 99, 4, 0, 0) 544 #define PTD3_FXIO_D7_O NXP_S32_PINMUX(0, 0, 99, 5, 0, 0) 545 #define PTD3_FXIO_D5_I NXP_S32_PINMUX(0, 0, 99, 0, 157, 2) 546 #define PTD3_FXIO_D7_I NXP_S32_PINMUX(0, 0, 99, 0, 159, 3) 547 #define PTD5_FXIO_D15_O NXP_S32_PINMUX(0, 0, 101, 6, 0, 0) 548 #define PTD5_FXIO_D15_I NXP_S32_PINMUX(0, 0, 101, 0, 167, 4) 549 #define PTD6_FXIO_D13_O NXP_S32_PINMUX(0, 0, 102, 6, 0, 0) 550 #define PTD6_FXIO_D13_I NXP_S32_PINMUX(0, 0, 102, 0, 165, 1) 551 #define PTD8_FXIO_D1_O NXP_S32_PINMUX(0, 0, 104, 5, 0, 0) 552 #define PTD8_FXIO_D11_O NXP_S32_PINMUX(0, 0, 104, 7, 0, 0) 553 #define PTD8_FXIO_D1_I NXP_S32_PINMUX(0, 0, 104, 0, 153, 5) 554 #define PTD8_FXIO_D11_I NXP_S32_PINMUX(0, 0, 104, 0, 163, 5) 555 #define PTD9_FXIO_D0_O NXP_S32_PINMUX(0, 0, 105, 3, 0, 0) 556 #define PTD9_FXIO_D10_O NXP_S32_PINMUX(0, 0, 105, 7, 0, 0) 557 #define PTD9_FXIO_D0_I NXP_S32_PINMUX(0, 0, 105, 0, 152, 5) 558 #define PTD9_FXIO_D10_I NXP_S32_PINMUX(0, 0, 105, 0, 162, 4) 559 #define PTD13_FXIO_D7_O NXP_S32_PINMUX(0, 0, 109, 3, 0, 0) 560 #define PTD13_FXIO_D7_I NXP_S32_PINMUX(0, 0, 109, 0, 159, 7) 561 #define PTD15_FXIO_D6_O NXP_S32_PINMUX(0, 0, 111, 1, 0, 0) 562 #define PTD15_FXIO_D10_O NXP_S32_PINMUX(0, 0, 111, 7, 0, 0) 563 #define PTD15_FXIO_D6_I NXP_S32_PINMUX(0, 0, 111, 0, 158, 7) 564 #define PTD15_FXIO_D10_I NXP_S32_PINMUX(0, 0, 111, 0, 162, 1) 565 #define PTD17_FXIO_D9_O NXP_S32_PINMUX(0, 0, 113, 6, 0, 0) 566 #define PTD17_FXIO_D9_I NXP_S32_PINMUX(0, 0, 113, 0, 161, 1) 567 #define PTD18_FXIO_D2_O NXP_S32_PINMUX(0, 0, 114, 3, 0, 0) 568 #define PTD18_FXIO_D2_I NXP_S32_PINMUX(0, 0, 114, 0, 154, 4) 569 #define PTD19_FXIO_D3_O NXP_S32_PINMUX(0, 0, 115, 3, 0, 0) 570 #define PTD19_FXIO_D3_I NXP_S32_PINMUX(0, 0, 115, 0, 155, 4) 571 #define PTD20_FXIO_D25_O NXP_S32_PINMUX(0, 0, 116, 3, 0, 0) 572 #define PTD20_FXIO_D25_I NXP_S32_PINMUX(0, 0, 116, 0, 177, 2) 573 #define PTD21_FXIO_D26_O NXP_S32_PINMUX(0, 0, 117, 3, 0, 0) 574 #define PTD21_FXIO_D26_I NXP_S32_PINMUX(0, 0, 117, 0, 178, 2) 575 #define PTD22_FXIO_D27_O NXP_S32_PINMUX(0, 0, 118, 3, 0, 0) 576 #define PTD22_FXIO_D27_I NXP_S32_PINMUX(0, 0, 118, 0, 179, 2) 577 #define PTD23_FXIO_D28_O NXP_S32_PINMUX(0, 0, 119, 3, 0, 0) 578 #define PTD23_FXIO_D28_I NXP_S32_PINMUX(0, 0, 119, 0, 180, 2) 579 #define PTD24_FXIO_D29_O NXP_S32_PINMUX(0, 0, 120, 3, 0, 0) 580 #define PTD24_FXIO_D29_I NXP_S32_PINMUX(0, 0, 120, 0, 181, 2) 581 #define PTD26_FXIO_D7_O NXP_S32_PINMUX(0, 0, 122, 3, 0, 0) 582 #define PTD26_FXIO_D30_O NXP_S32_PINMUX(0, 0, 122, 5, 0, 0) 583 #define PTD26_FXIO_D7_I NXP_S32_PINMUX(0, 0, 122, 0, 159, 4) 584 #define PTD26_FXIO_D30_I NXP_S32_PINMUX(0, 0, 122, 0, 182, 2) 585 #define PTD27_FXIO_D31_O NXP_S32_PINMUX(0, 0, 123, 5, 0, 0) 586 #define PTD27_FXIO_D31_I NXP_S32_PINMUX(0, 0, 123, 0, 183, 2) 587 #define PTD31_FXIO_D6_O NXP_S32_PINMUX(0, 0, 127, 3, 0, 0) 588 #define PTD31_FXIO_D6_I NXP_S32_PINMUX(0, 0, 127, 0, 158, 4) 589 #define PTE0_FXIO_D3_O NXP_S32_PINMUX(0, 0, 128, 3, 0, 0) 590 #define PTE0_FXIO_D3_I NXP_S32_PINMUX(0, 0, 128, 0, 155, 7) 591 #define PTE1_FXIO_D2_O NXP_S32_PINMUX(0, 0, 129, 3, 0, 0) 592 #define PTE1_FXIO_D2_I NXP_S32_PINMUX(0, 0, 129, 0, 154, 8) 593 #define PTE2_FXIO_D13_O NXP_S32_PINMUX(0, 0, 130, 6, 0, 0) 594 #define PTE2_FXIO_D13_I NXP_S32_PINMUX(0, 0, 130, 0, 165, 4) 595 #define PTE3_FXIO_D6_O NXP_S32_PINMUX(0, 0, 131, 4, 0, 0) 596 #define PTE3_FXIO_D6_I NXP_S32_PINMUX(0, 0, 131, 0, 158, 6) 597 #define PTE4_FXIO_D6_O NXP_S32_PINMUX(0, 0, 132, 6, 0, 0) 598 #define PTE4_FXIO_D6_I NXP_S32_PINMUX(0, 0, 132, 0, 158, 1) 599 #define PTE5_FXIO_D7_O NXP_S32_PINMUX(0, 0, 133, 6, 0, 0) 600 #define PTE5_FXIO_D7_I NXP_S32_PINMUX(0, 0, 133, 0, 159, 1) 601 #define PTE6_FXIO_D12_O NXP_S32_PINMUX(0, 0, 134, 6, 0, 0) 602 #define PTE6_FXIO_D12_I NXP_S32_PINMUX(0, 0, 134, 0, 164, 4) 603 #define PTE7_FXIO_D11_O NXP_S32_PINMUX(0, 0, 135, 7, 0, 0) 604 #define PTE7_FXIO_D11_I NXP_S32_PINMUX(0, 0, 135, 0, 163, 4) 605 #define PTE8_FXIO_D12_O NXP_S32_PINMUX(0, 0, 136, 4, 0, 0) 606 #define PTE8_FXIO_D8_O NXP_S32_PINMUX(0, 0, 136, 7, 0, 0) 607 #define PTE8_FXIO_D8_I NXP_S32_PINMUX(0, 0, 136, 0, 160, 5) 608 #define PTE8_FXIO_D12_I NXP_S32_PINMUX(0, 0, 136, 0, 164, 1) 609 #define PTE9_FXIO_D11_O NXP_S32_PINMUX(0, 0, 137, 7, 0, 0) 610 #define PTE9_FXIO_D11_I NXP_S32_PINMUX(0, 0, 137, 0, 163, 1) 611 #define PTE10_FXIO_D4_O NXP_S32_PINMUX(0, 0, 138, 6, 0, 0) 612 #define PTE10_FXIO_D4_I NXP_S32_PINMUX(0, 0, 138, 0, 156, 2) 613 #define PTE11_FXIO_D5_O NXP_S32_PINMUX(0, 0, 139, 6, 0, 0) 614 #define PTE11_FXIO_D5_I NXP_S32_PINMUX(0, 0, 139, 0, 157, 1) 615 #define PTE12_FXIO_D8_O NXP_S32_PINMUX(0, 0, 140, 6, 0, 0) 616 #define PTE12_FXIO_D8_I NXP_S32_PINMUX(0, 0, 140, 0, 160, 1) 617 #define PTE13_FXIO_D5_O NXP_S32_PINMUX(0, 0, 141, 6, 0, 0) 618 #define PTE13_FXIO_D5_I NXP_S32_PINMUX(0, 0, 141, 0, 157, 5) 619 #define PTE14_FXIO_D7_O NXP_S32_PINMUX(0, 0, 142, 6, 0, 0) 620 #define PTE14_FXIO_D7_I NXP_S32_PINMUX(0, 0, 142, 0, 159, 5) 621 #define PTE15_FXIO_D2_O NXP_S32_PINMUX(0, 0, 143, 6, 0, 0) 622 #define PTE15_FXIO_D2_I NXP_S32_PINMUX(0, 0, 143, 0, 154, 1) 623 #define PTE16_FXIO_D3_O NXP_S32_PINMUX(0, 0, 144, 6, 0, 0) 624 #define PTE16_FXIO_D3_I NXP_S32_PINMUX(0, 0, 144, 0, 155, 2) 625 #define PTE17_FXIO_D5_O NXP_S32_PINMUX(0, 0, 145, 3, 0, 0) 626 #define PTE17_FXIO_D5_I NXP_S32_PINMUX(0, 0, 145, 0, 157, 4) 627 #define PTE18_FXIO_D4_O NXP_S32_PINMUX(0, 0, 146, 3, 0, 0) 628 #define PTE18_FXIO_D4_I NXP_S32_PINMUX(0, 0, 146, 0, 156, 4) 629 #define PTE24_FXIO_D5_O NXP_S32_PINMUX(0, 0, 152, 5, 0, 0) 630 #define PTE24_FXIO_D11_O NXP_S32_PINMUX(0, 0, 152, 7, 0, 0) 631 #define PTE24_FXIO_D5_I NXP_S32_PINMUX(0, 0, 152, 0, 157, 10) 632 #define PTE24_FXIO_D11_I NXP_S32_PINMUX(0, 0, 152, 0, 163, 6) 633 #define PTF4_FXIO_D0_O NXP_S32_PINMUX(0, 0, 164, 4, 0, 0) 634 #define PTF4_FXIO_D0_I NXP_S32_PINMUX(0, 0, 164, 0, 152, 7) 635 #define PTF7_FXIO_D1_O NXP_S32_PINMUX(0, 0, 167, 4, 0, 0) 636 #define PTF7_FXIO_D1_I NXP_S32_PINMUX(0, 0, 167, 0, 153, 8) 637 #define PTF8_FXIO_D2_O NXP_S32_PINMUX(0, 0, 168, 4, 0, 0) 638 #define PTF8_FXIO_D2_I NXP_S32_PINMUX(0, 0, 168, 0, 154, 9) 639 #define PTF14_FXIO_D3_O NXP_S32_PINMUX(0, 0, 174, 5, 0, 0) 640 #define PTF14_FXIO_D3_I NXP_S32_PINMUX(0, 0, 174, 0, 155, 8) 641 #define PTF20_FXIO_D4_O NXP_S32_PINMUX(0, 0, 180, 7, 0, 0) 642 #define PTF20_FXIO_D4_I NXP_S32_PINMUX(0, 0, 180, 0, 156, 8) 643 #define PTF21_FXIO_D5_O NXP_S32_PINMUX(0, 0, 181, 7, 0, 0) 644 #define PTF21_FXIO_D5_I NXP_S32_PINMUX(0, 0, 181, 0, 157, 11) 645 #define PTF25_FXIO_D6_O NXP_S32_PINMUX(0, 0, 185, 7, 0, 0) 646 #define PTF25_FXIO_D6_I NXP_S32_PINMUX(0, 0, 185, 0, 158, 10) 647 #define PTF28_FXIO_D7_O NXP_S32_PINMUX(0, 0, 188, 4, 0, 0) 648 #define PTF28_FXIO_D7_I NXP_S32_PINMUX(0, 0, 188, 0, 159, 8) 649 #define PTF29_FXIO_D8_O NXP_S32_PINMUX(0, 0, 189, 7, 0, 0) 650 #define PTF29_FXIO_D8_I NXP_S32_PINMUX(0, 0, 189, 0, 160, 6) 651 #define PTF31_FXIO_D9_O NXP_S32_PINMUX(0, 0, 191, 6, 0, 0) 652 #define PTF31_FXIO_D9_I NXP_S32_PINMUX(0, 0, 191, 0, 161, 5) 653 #define PTG6_FXIO_D10_O NXP_S32_PINMUX(0, 0, 198, 2, 0, 0) 654 #define PTG6_FXIO_D10_I NXP_S32_PINMUX(0, 0, 198, 0, 162, 5) 655 #define PTG7_FXIO_D11_O NXP_S32_PINMUX(0, 0, 199, 2, 0, 0) 656 #define PTG7_FXIO_D11_I NXP_S32_PINMUX(0, 0, 199, 0, 163, 7) 657 #define PTG8_FXIO_D12_O NXP_S32_PINMUX(0, 0, 200, 2, 0, 0) 658 #define PTG8_FXIO_D12_I NXP_S32_PINMUX(0, 0, 200, 0, 164, 5) 659 #define PTG13_FXIO_D13_O NXP_S32_PINMUX(0, 0, 205, 2, 0, 0) 660 #define PTG13_FXIO_D13_I NXP_S32_PINMUX(0, 0, 205, 0, 165, 5) 661 #define PTG15_FXIO_D14_O NXP_S32_PINMUX(0, 0, 207, 2, 0, 0) 662 #define PTG15_FXIO_D14_I NXP_S32_PINMUX(0, 0, 207, 0, 166, 5) 663 #define PTG16_FXIO_D15_O NXP_S32_PINMUX(0, 0, 208, 3, 0, 0) 664 #define PTG16_FXIO_D15_I NXP_S32_PINMUX(0, 0, 208, 0, 167, 6) 665 #define PTG17_FXIO_D16_O NXP_S32_PINMUX(0, 0, 209, 3, 0, 0) 666 #define PTG17_FXIO_D16_I NXP_S32_PINMUX(0, 0, 209, 0, 168, 4) 667 #define PTG18_FXIO_D17_O NXP_S32_PINMUX(0, 0, 210, 3, 0, 0) 668 #define PTG18_FXIO_D17_I NXP_S32_PINMUX(0, 0, 210, 0, 169, 3) 669 #define PTG19_FXIO_D18_O NXP_S32_PINMUX(0, 0, 211, 3, 0, 0) 670 #define PTG19_FXIO_D18_I NXP_S32_PINMUX(0, 0, 211, 0, 170, 3) 671 #define PTG20_FXIO_D19_O NXP_S32_PINMUX(0, 0, 212, 3, 0, 0) 672 #define PTG20_FXIO_D19_I NXP_S32_PINMUX(0, 0, 212, 0, 171, 6) 673 #define PTG21_FXIO_D20_O NXP_S32_PINMUX(0, 0, 213, 3, 0, 0) 674 #define PTG21_FXIO_D20_I NXP_S32_PINMUX(0, 0, 213, 0, 172, 3) 675 #define PTG22_FXIO_D21_O NXP_S32_PINMUX(0, 0, 214, 3, 0, 0) 676 #define PTG22_FXIO_D21_I NXP_S32_PINMUX(0, 0, 214, 0, 173, 3) 677 #define PTG23_FXIO_D22_O NXP_S32_PINMUX(0, 0, 215, 3, 0, 0) 678 #define PTG23_FXIO_D22_I NXP_S32_PINMUX(0, 0, 215, 0, 174, 3) 679 #define PTG24_FXIO_D23_O NXP_S32_PINMUX(0, 0, 216, 3, 0, 0) 680 #define PTG24_FXIO_D23_I NXP_S32_PINMUX(0, 0, 216, 0, 175, 3) 681 #define PTG25_FXIO_D24_O NXP_S32_PINMUX(0, 0, 217, 3, 0, 0) 682 #define PTG25_FXIO_D24_I NXP_S32_PINMUX(0, 0, 217, 0, 176, 3) 683 #define PTG26_FXIO_D25_O NXP_S32_PINMUX(0, 0, 218, 3, 0, 0) 684 #define PTG26_FXIO_D25_I NXP_S32_PINMUX(0, 0, 218, 0, 177, 3) 685 #define PTG27_FXIO_D26_O NXP_S32_PINMUX(0, 0, 219, 3, 0, 0) 686 #define PTG27_FXIO_D26_I NXP_S32_PINMUX(0, 0, 219, 0, 178, 3) 687 688 /* EMIOS_1 */ 689 #define PTA0_EMIOS_1_CH0_X_O NXP_S32_PINMUX(0, 0, 0, 5, 0, 0) 690 #define PTA0_EMIOS_1_CH0_X_I NXP_S32_PINMUX(0, 0, 0, 0, 80, 3) 691 #define PTA2_EMIOS_1_CH19_Y_O NXP_S32_PINMUX(0, 0, 2, 2, 0, 0) 692 #define PTA2_EMIOS_1_CH19_Y_I NXP_S32_PINMUX(0, 0, 2, 0, 99, 4) 693 #define PTA3_EMIOS_1_CH20_Y_O NXP_S32_PINMUX(0, 0, 3, 2, 0, 0) 694 #define PTA3_EMIOS_1_CH20_Y_I NXP_S32_PINMUX(0, 0, 3, 0, 100, 4) 695 #define PTA6_EMIOS_1_CH13_H_O NXP_S32_PINMUX(0, 0, 6, 4, 0, 0) 696 #define PTA6_EMIOS_1_CH13_H_I NXP_S32_PINMUX(0, 0, 6, 0, 93, 1) 697 #define PTA7_EMIOS_1_CH11_H_O NXP_S32_PINMUX(0, 0, 7, 3, 0, 0) 698 #define PTA7_EMIOS_1_CH11_H_I NXP_S32_PINMUX(0, 0, 7, 0, 91, 1) 699 #define PTA8_EMIOS_1_CH12_H_O NXP_S32_PINMUX(0, 0, 8, 2, 0, 0) 700 #define PTA8_EMIOS_1_CH12_H_I NXP_S32_PINMUX(0, 0, 8, 0, 92, 2) 701 #define PTA11_EMIOS_1_CH1_H_O NXP_S32_PINMUX(0, 0, 11, 3, 0, 0) 702 #define PTA11_EMIOS_1_CH1_H_I NXP_S32_PINMUX(0, 0, 11, 0, 81, 3) 703 #define PTA12_EMIOS_1_CH2_H_O NXP_S32_PINMUX(0, 0, 12, 6, 0, 0) 704 #define PTA12_EMIOS_1_CH2_H_I NXP_S32_PINMUX(0, 0, 12, 0, 82, 4) 705 #define PTA13_EMIOS_1_CH3_H_O NXP_S32_PINMUX(0, 0, 13, 6, 0, 0) 706 #define PTA13_EMIOS_1_CH3_H_I NXP_S32_PINMUX(0, 0, 13, 0, 83, 4) 707 #define PTA14_EMIOS_1_CH4_H_O NXP_S32_PINMUX(0, 0, 14, 2, 0, 0) 708 #define PTA14_EMIOS_1_CH4_H_I NXP_S32_PINMUX(0, 0, 14, 0, 84, 7) 709 #define PTA18_EMIOS_1_CH0_X_O NXP_S32_PINMUX(0, 0, 18, 2, 0, 0) 710 #define PTA18_EMIOS_1_CH16_X_O NXP_S32_PINMUX(0, 0, 18, 5, 0, 0) 711 #define PTA18_EMIOS_1_CH0_X_I NXP_S32_PINMUX(0, 0, 18, 0, 80, 1) 712 #define PTA18_EMIOS_1_CH16_X_I NXP_S32_PINMUX(0, 0, 18, 0, 96, 1) 713 #define PTA19_EMIOS_1_CH1_H_O NXP_S32_PINMUX(0, 0, 19, 2, 0, 0) 714 #define PTA19_EMIOS_1_CH1_H_I NXP_S32_PINMUX(0, 0, 19, 0, 81, 1) 715 #define PTA20_EMIOS_1_CH2_H_O NXP_S32_PINMUX(0, 0, 20, 2, 0, 0) 716 #define PTA20_EMIOS_1_CH2_H_I NXP_S32_PINMUX(0, 0, 20, 0, 82, 2) 717 #define PTA21_EMIOS_1_CH3_H_O NXP_S32_PINMUX(0, 0, 21, 2, 0, 0) 718 #define PTA21_EMIOS_1_CH3_H_I NXP_S32_PINMUX(0, 0, 21, 0, 83, 1) 719 #define PTA22_EMIOS_1_CH4_H_O NXP_S32_PINMUX(0, 0, 22, 2, 0, 0) 720 #define PTA22_EMIOS_1_CH4_H_I NXP_S32_PINMUX(0, 0, 22, 0, 84, 1) 721 #define PTA23_EMIOS_1_CH6_H_O NXP_S32_PINMUX(0, 0, 23, 2, 0, 0) 722 #define PTA23_EMIOS_1_CH6_H_I NXP_S32_PINMUX(0, 0, 23, 0, 86, 2) 723 #define PTA24_EMIOS_1_CH7_H NXP_S32_PINMUX(0, 0, 23, 0, 87, 2) 724 #define PTA25_EMIOS_1_CH8_X NXP_S32_PINMUX(0, 0, 23, 0, 88, 2) 725 #define PTA26_EMIOS_1_CH9_H_O NXP_S32_PINMUX(0, 0, 26, 2, 0, 0) 726 #define PTA26_EMIOS_1_CH9_H_I NXP_S32_PINMUX(0, 0, 26, 0, 89, 2) 727 #define PTA27_EMIOS_1_CH10_H_O NXP_S32_PINMUX(0, 0, 27, 2, 0, 0) 728 #define PTA27_EMIOS_1_CH10_H_I NXP_S32_PINMUX(0, 0, 27, 0, 90, 3) 729 #define PTA28_EMIOS_1_CH11_H_O NXP_S32_PINMUX(0, 0, 28, 2, 0, 0) 730 #define PTA28_EMIOS_1_CH11_H_I NXP_S32_PINMUX(0, 0, 28, 0, 91, 2) 731 #define PTA29_EMIOS_1_CH12_H_O NXP_S32_PINMUX(0, 0, 29, 2, 0, 0) 732 #define PTA29_EMIOS_1_CH12_H_I NXP_S32_PINMUX(0, 0, 29, 0, 92, 3) 733 #define PTA30_EMIOS_1_CH13_H_O NXP_S32_PINMUX(0, 0, 30, 2, 0, 0) 734 #define PTA30_EMIOS_1_CH13_H_I NXP_S32_PINMUX(0, 0, 30, 0, 93, 2) 735 #define PTA31_EMIOS_1_CH14_H_O NXP_S32_PINMUX(0, 0, 31, 2, 0, 0) 736 #define PTA31_EMIOS_1_CH14_H_I NXP_S32_PINMUX(0, 0, 31, 0, 94, 2) 737 #define PTB0_EMIOS_1_CH6_H_O NXP_S32_PINMUX(0, 0, 32, 6, 0, 0) 738 #define PTB0_EMIOS_1_CH6_H_I NXP_S32_PINMUX(0, 0, 32, 0, 86, 1) 739 #define PTB1_EMIOS_1_CH5_H_O NXP_S32_PINMUX(0, 0, 33, 6, 0, 0) 740 #define PTB1_EMIOS_1_CH5_H_I NXP_S32_PINMUX(0, 0, 33, 0, 85, 1) 741 #define PTB4_EMIOS_1_CH10_H_O NXP_S32_PINMUX(0, 0, 36, 6, 0, 0) 742 #define PTB4_EMIOS_1_CH10_H_I NXP_S32_PINMUX(0, 0, 36, 0, 90, 6) 743 #define PTB5_EMIOS_1_CH11_H_O NXP_S32_PINMUX(0, 0, 37, 6, 0, 0) 744 #define PTB5_EMIOS_1_CH11_H_I NXP_S32_PINMUX(0, 0, 37, 0, 91, 5) 745 #define PTB8_EMIOS_1_CH15_H_O NXP_S32_PINMUX(0, 0, 40, 2, 0, 0) 746 #define PTB8_EMIOS_1_CH15_H_I NXP_S32_PINMUX(0, 0, 40, 0, 95, 6) 747 #define PTB9_EMIOS_1_CH16_X_O NXP_S32_PINMUX(0, 0, 41, 2, 0, 0) 748 #define PTB9_EMIOS_1_CH16_X_I NXP_S32_PINMUX(0, 0, 41, 0, 96, 5) 749 #define PTB10_EMIOS_1_CH17_Y_O NXP_S32_PINMUX(0, 0, 42, 2, 0, 0) 750 #define PTB10_EMIOS_1_CH17_Y_I NXP_S32_PINMUX(0, 0, 42, 0, 97, 4) 751 #define PTB11_EMIOS_1_CH18_Y_O NXP_S32_PINMUX(0, 0, 43, 2, 0, 0) 752 #define PTB11_EMIOS_1_CH18_Y_I NXP_S32_PINMUX(0, 0, 43, 0, 98, 4) 753 #define PTB17_EMIOS_1_CH7_H_O NXP_S32_PINMUX(0, 0, 49, 4, 0, 0) 754 #define PTB17_EMIOS_1_CH7_H_I NXP_S32_PINMUX(0, 0, 49, 0, 87, 7) 755 #define PTB18_EMIOS_1_CH15_H_O NXP_S32_PINMUX(0, 0, 50, 2, 0, 0) 756 #define PTB18_EMIOS_1_CH15_H_I NXP_S32_PINMUX(0, 0, 50, 0, 95, 2) 757 #define PTB19_EMIOS_1_CH15_H_O NXP_S32_PINMUX(0, 0, 51, 2, 0, 0) 758 #define PTB19_EMIOS_1_CH15_H_I NXP_S32_PINMUX(0, 0, 51, 0, 95, 3) 759 #define PTB20_EMIOS_1_CH16_X_O NXP_S32_PINMUX(0, 0, 52, 2, 0, 0) 760 #define PTB20_EMIOS_1_CH16_X_I NXP_S32_PINMUX(0, 0, 52, 0, 96, 3) 761 #define PTB21_EMIOS_1_CH17_Y_O NXP_S32_PINMUX(0, 0, 53, 2, 0, 0) 762 #define PTB21_EMIOS_1_CH17_Y_I NXP_S32_PINMUX(0, 0, 53, 0, 97, 2) 763 #define PTB22_EMIOS_1_CH18_Y_O NXP_S32_PINMUX(0, 0, 54, 2, 0, 0) 764 #define PTB22_EMIOS_1_CH18_Y_I NXP_S32_PINMUX(0, 0, 54, 0, 98, 2) 765 #define PTB23_EMIOS_1_CH19_Y_O NXP_S32_PINMUX(0, 0, 55, 2, 0, 0) 766 #define PTB23_EMIOS_1_CH19_Y_I NXP_S32_PINMUX(0, 0, 55, 0, 99, 2) 767 #define PTB24_EMIOS_1_CH20_Y_O NXP_S32_PINMUX(0, 0, 56, 2, 0, 0) 768 #define PTB24_EMIOS_1_CH20_Y_I NXP_S32_PINMUX(0, 0, 56, 0, 100, 2) 769 #define PTB25_EMIOS_1_CH21_Y_O NXP_S32_PINMUX(0, 0, 57, 2, 0, 0) 770 #define PTB25_EMIOS_1_CH21_Y_I NXP_S32_PINMUX(0, 0, 57, 0, 101, 2) 771 #define PTB26_EMIOS_1_CH22_X_O NXP_S32_PINMUX(0, 0, 58, 2, 0, 0) 772 #define PTB26_EMIOS_1_CH22_X_I NXP_S32_PINMUX(0, 0, 58, 0, 102, 2) 773 #define PTB27_EMIOS_1_CH23_X_O NXP_S32_PINMUX(0, 0, 59, 2, 0, 0) 774 #define PTB27_EMIOS_1_CH23_X_I NXP_S32_PINMUX(0, 0, 59, 0, 103, 2) 775 #define PTC6_EMIOS_1_CH6_H_O NXP_S32_PINMUX(0, 0, 70, 5, 0, 0) 776 #define PTC6_EMIOS_1_CH6_H_I NXP_S32_PINMUX(0, 0, 70, 0, 86, 4) 777 #define PTC7_EMIOS_1_CH7_H_O NXP_S32_PINMUX(0, 0, 71, 5, 0, 0) 778 #define PTC7_EMIOS_1_CH7_H_I NXP_S32_PINMUX(0, 0, 71, 0, 87, 4) 779 #define PTC8_EMIOS_1_CH9_H_O NXP_S32_PINMUX(0, 0, 72, 4, 0, 0) 780 #define PTC8_EMIOS_1_CH9_H_I NXP_S32_PINMUX(0, 0, 72, 0, 89, 1) 781 #define PTC9_EMIOS_1_CH8_X_O NXP_S32_PINMUX(0, 0, 73, 4, 0, 0) 782 #define PTC9_EMIOS_1_CH8_X_I NXP_S32_PINMUX(0, 0, 73, 0, 88, 1) 783 #define PTC10_EMIOS_1_CH0_X_O NXP_S32_PINMUX(0, 0, 74, 7, 0, 0) 784 #define PTC10_EMIOS_1_CH0_X_I NXP_S32_PINMUX(0, 0, 74, 0, 80, 6) 785 #define PTC11_EMIOS_1_CH1_H_O NXP_S32_PINMUX(0, 0, 75, 3, 0, 0) 786 #define PTC11_EMIOS_1_CH1_H_I NXP_S32_PINMUX(0, 0, 75, 0, 81, 7) 787 #define PTC12_EMIOS_1_CH2_H_O NXP_S32_PINMUX(0, 0, 76, 2, 0, 0) 788 #define PTC12_EMIOS_1_CH2_H_I NXP_S32_PINMUX(0, 0, 76, 0, 82, 1) 789 #define PTC13_EMIOS_1_CH3_H_O NXP_S32_PINMUX(0, 0, 77, 2, 0, 0) 790 #define PTC13_EMIOS_1_CH3_H_I NXP_S32_PINMUX(0, 0, 77, 0, 83, 7) 791 #define PTC14_EMIOS_1_CH4_H_O NXP_S32_PINMUX(0, 0, 78, 5, 0, 0) 792 #define PTC14_EMIOS_1_CH4_H_I NXP_S32_PINMUX(0, 0, 78, 0, 84, 8) 793 #define PTC16_EMIOS_1_CH9_H_O NXP_S32_PINMUX(0, 0, 80, 2, 0, 0) 794 #define PTC16_EMIOS_1_CH9_H_I NXP_S32_PINMUX(0, 0, 80, 0, 89, 5) 795 #define PTC24_EMIOS_1_CH0_X_O NXP_S32_PINMUX(0, 0, 88, 2, 0, 0) 796 #define PTC24_EMIOS_1_CH0_X_I NXP_S32_PINMUX(0, 0, 88, 0, 80, 4) 797 #define PTC25_EMIOS_1_CH1_H_O NXP_S32_PINMUX(0, 0, 89, 2, 0, 0) 798 #define PTC25_EMIOS_1_CH1_H_I NXP_S32_PINMUX(0, 0, 89, 0, 81, 4) 799 #define PTC26_EMIOS_1_CH3_H_O NXP_S32_PINMUX(0, 0, 90, 2, 0, 0) 800 #define PTC26_EMIOS_1_CH3_H_I NXP_S32_PINMUX(0, 0, 90, 0, 83, 3) 801 #define PTC27_EMIOS_1_CH4_H_O NXP_S32_PINMUX(0, 0, 91, 2, 0, 0) 802 #define PTC27_EMIOS_1_CH4_H_I NXP_S32_PINMUX(0, 0, 91, 0, 84, 2) 803 #define PTC28_EMIOS_1_CH7_H_O NXP_S32_PINMUX(0, 0, 92, 2, 0, 0) 804 #define PTC28_EMIOS_1_CH7_H_I NXP_S32_PINMUX(0, 0, 92, 0, 87, 3) 805 #define PTC29_EMIOS_1_CH10_H_O NXP_S32_PINMUX(0, 0, 93, 2, 0, 0) 806 #define PTC29_EMIOS_1_CH10_H_I NXP_S32_PINMUX(0, 0, 93, 0, 90, 1) 807 #define PTC30_EMIOS_1_CH12_H_O NXP_S32_PINMUX(0, 0, 94, 2, 0, 0) 808 #define PTC30_EMIOS_1_CH12_H_I NXP_S32_PINMUX(0, 0, 94, 0, 92, 1) 809 #define PTC31_EMIOS_1_CH14_H_O NXP_S32_PINMUX(0, 0, 95, 2, 0, 0) 810 #define PTC31_EMIOS_1_CH14_H_I NXP_S32_PINMUX(0, 0, 95, 0, 94, 1) 811 #define PTD2_EMIOS_1_CH21_Y_O NXP_S32_PINMUX(0, 0, 98, 2, 0, 0) 812 #define PTD2_EMIOS_1_CH21_Y_I NXP_S32_PINMUX(0, 0, 98, 0, 101, 4) 813 #define PTD3_EMIOS_1_CH22_X_O NXP_S32_PINMUX(0, 0, 99, 2, 0, 0) 814 #define PTD3_EMIOS_1_CH22_X_I NXP_S32_PINMUX(0, 0, 99, 0, 102, 4) 815 #define PTD4_EMIOS_1_CH23_X_O NXP_S32_PINMUX(0, 0, 100, 2, 0, 0) 816 #define PTD4_EMIOS_1_CH23_X_I NXP_S32_PINMUX(0, 0, 100, 0, 103, 4) 817 #define PTD6_EMIOS_1_CH12_H_O NXP_S32_PINMUX(0, 0, 102, 3, 0, 0) 818 #define PTD6_EMIOS_1_CH12_H_I NXP_S32_PINMUX(0, 0, 102, 0, 92, 5) 819 #define PTD10_EMIOS_1_CH10_H_O NXP_S32_PINMUX(0, 0, 106, 3, 0, 0) 820 #define PTD10_EMIOS_1_CH10_H_I NXP_S32_PINMUX(0, 0, 106, 0, 90, 2) 821 #define PTD15_EMIOS_1_CH14_H_O NXP_S32_PINMUX(0, 0, 111, 3, 0, 0) 822 #define PTD15_EMIOS_1_CH14_H_I NXP_S32_PINMUX(0, 0, 111, 0, 94, 6) 823 #define PTD16_EMIOS_1_CH15_H_O NXP_S32_PINMUX(0, 0, 112, 5, 0, 0) 824 #define PTD16_EMIOS_1_CH15_H_I NXP_S32_PINMUX(0, 0, 112, 0, 95, 7) 825 #define PTD18_EMIOS_1_CH15_H_O NXP_S32_PINMUX(0, 0, 114, 2, 0, 0) 826 #define PTD18_EMIOS_1_CH15_H_I NXP_S32_PINMUX(0, 0, 114, 0, 95, 1) 827 #define PTD19_EMIOS_1_CH16_X_O NXP_S32_PINMUX(0, 0, 115, 2, 0, 0) 828 #define PTD19_EMIOS_1_CH16_X_I NXP_S32_PINMUX(0, 0, 115, 0, 96, 2) 829 #define PTD20_EMIOS_1_CH17_Y_O NXP_S32_PINMUX(0, 0, 116, 2, 0, 0) 830 #define PTD20_EMIOS_1_CH17_Y_I NXP_S32_PINMUX(0, 0, 116, 0, 97, 1) 831 #define PTD21_EMIOS_1_CH18_Y_O NXP_S32_PINMUX(0, 0, 117, 2, 0, 0) 832 #define PTD21_EMIOS_1_CH18_Y_I NXP_S32_PINMUX(0, 0, 117, 0, 98, 1) 833 #define PTD22_EMIOS_1_CH19_Y_O NXP_S32_PINMUX(0, 0, 118, 2, 0, 0) 834 #define PTD22_EMIOS_1_CH19_Y_I NXP_S32_PINMUX(0, 0, 118, 0, 99, 1) 835 #define PTD23_EMIOS_1_CH20_Y_O NXP_S32_PINMUX(0, 0, 119, 2, 0, 0) 836 #define PTD23_EMIOS_1_CH20_Y_I NXP_S32_PINMUX(0, 0, 119, 0, 100, 1) 837 #define PTD24_EMIOS_1_CH21_Y_O NXP_S32_PINMUX(0, 0, 120, 2, 0, 0) 838 #define PTD24_EMIOS_1_CH21_Y_I NXP_S32_PINMUX(0, 0, 120, 0, 101, 1) 839 #define PTD25_EMIOS_1_CH22_X_O NXP_S32_PINMUX(0, 0, 121, 2, 0, 0) 840 #define PTD25_EMIOS_1_CH22_X_I NXP_S32_PINMUX(0, 0, 121, 0, 102, 1) 841 #define PTD26_EMIOS_1_CH23_X_O NXP_S32_PINMUX(0, 0, 122, 2, 0, 0) 842 #define PTD26_EMIOS_1_CH23_X_I NXP_S32_PINMUX(0, 0, 122, 0, 103, 1) 843 #define PTE2_EMIOS_1_CH8_X_O NXP_S32_PINMUX(0, 0, 130, 4, 0, 0) 844 #define PTE2_EMIOS_1_CH8_X_I NXP_S32_PINMUX(0, 0, 130, 0, 88, 4) 845 #define PTE4_EMIOS_1_CH4_H_O NXP_S32_PINMUX(0, 0, 132, 3, 0, 0) 846 #define PTE4_EMIOS_1_CH4_H_I NXP_S32_PINMUX(0, 0, 132, 0, 84, 4) 847 #define PTE5_EMIOS_1_CH5_H_O NXP_S32_PINMUX(0, 0, 133, 3, 0, 0) 848 #define PTE5_EMIOS_1_CH5_H_I NXP_S32_PINMUX(0, 0, 133, 0, 85, 4) 849 #define PTE6_EMIOS_1_CH14_H_O NXP_S32_PINMUX(0, 0, 134, 4, 0, 0) 850 #define PTE6_EMIOS_1_CH14_H_I NXP_S32_PINMUX(0, 0, 134, 0, 94, 5) 851 #define PTE9_EMIOS_1_CH13_H_O NXP_S32_PINMUX(0, 0, 137, 3, 0, 0) 852 #define PTE9_EMIOS_1_CH13_H_I NXP_S32_PINMUX(0, 0, 137, 0, 93, 5) 853 #define PTE12_EMIOS_1_CH5_H_O NXP_S32_PINMUX(0, 0, 140, 4, 0, 0) 854 #define PTE12_EMIOS_1_CH5_H_I NXP_S32_PINMUX(0, 0, 140, 0, 85, 5) 855 #define PTE13_EMIOS_1_CH5_H_O NXP_S32_PINMUX(0, 0, 141, 2, 0, 0) 856 #define PTE13_EMIOS_1_CH5_H_I NXP_S32_PINMUX(0, 0, 141, 0, 85, 3) 857 #define PTE20_EMIOS_1_CH0_X_O NXP_S32_PINMUX(0, 0, 148, 2, 0, 0) 858 #define PTE20_EMIOS_1_CH0_X_I NXP_S32_PINMUX(0, 0, 148, 0, 80, 2) 859 #define PTE21_EMIOS_1_CH1_H_O NXP_S32_PINMUX(0, 0, 149, 2, 0, 0) 860 #define PTE21_EMIOS_1_CH1_H_I NXP_S32_PINMUX(0, 0, 149, 0, 81, 2) 861 #define PTE22_EMIOS_1_CH2_H_O NXP_S32_PINMUX(0, 0, 150, 2, 0, 0) 862 #define PTE22_EMIOS_1_CH2_H_I NXP_S32_PINMUX(0, 0, 150, 0, 82, 3) 863 #define PTE23_EMIOS_1_CH3_H_O NXP_S32_PINMUX(0, 0, 151, 2, 0, 0) 864 #define PTE23_EMIOS_1_CH3_H_I NXP_S32_PINMUX(0, 0, 151, 0, 83, 2) 865 #define PTE24_EMIOS_1_CH4_H_O NXP_S32_PINMUX(0, 0, 152, 2, 0, 0) 866 #define PTE24_EMIOS_1_CH4_H_I NXP_S32_PINMUX(0, 0, 152, 0, 84, 3) 867 #define PTE25_EMIOS_1_CH5_H_O NXP_S32_PINMUX(0, 0, 153, 2, 0, 0) 868 #define PTE25_EMIOS_1_CH5_H_I NXP_S32_PINMUX(0, 0, 153, 0, 85, 2) 869 #define PTE26_EMIOS_1_CH6_H_O NXP_S32_PINMUX(0, 0, 154, 2, 0, 0) 870 #define PTE26_EMIOS_1_CH6_H_I NXP_S32_PINMUX(0, 0, 154, 0, 86, 3) 871 #define PTE27_EMIOS_1_CH7_H_O NXP_S32_PINMUX(0, 0, 155, 2, 0, 0) 872 #define PTE27_EMIOS_1_CH7_H_I NXP_S32_PINMUX(0, 0, 155, 0, 87, 1) 873 #define PTF16_EMIOS_1_CH0_X_O NXP_S32_PINMUX(0, 0, 176, 3, 0, 0) 874 #define PTF16_EMIOS_1_CH0_X_I NXP_S32_PINMUX(0, 0, 176, 0, 80, 5) 875 #define PTF17_EMIOS_1_CH1_H_O NXP_S32_PINMUX(0, 0, 177, 3, 0, 0) 876 #define PTF17_EMIOS_1_CH1_H_I NXP_S32_PINMUX(0, 0, 177, 0, 81, 5) 877 #define PTF18_EMIOS_1_CH2_H_O NXP_S32_PINMUX(0, 0, 178, 3, 0, 0) 878 #define PTF18_EMIOS_1_CH2_H_I NXP_S32_PINMUX(0, 0, 178, 0, 82, 5) 879 #define PTF19_EMIOS_1_CH3_H_O NXP_S32_PINMUX(0, 0, 179, 3, 0, 0) 880 #define PTF19_EMIOS_1_CH3_H_I NXP_S32_PINMUX(0, 0, 179, 0, 83, 5) 881 #define PTF20_EMIOS_1_CH4_H_O NXP_S32_PINMUX(0, 0, 180, 3, 0, 0) 882 #define PTF20_EMIOS_1_CH4_H_I NXP_S32_PINMUX(0, 0, 180, 0, 84, 5) 883 #define PTF21_EMIOS_1_CH5_H_O NXP_S32_PINMUX(0, 0, 181, 3, 0, 0) 884 #define PTF21_EMIOS_1_CH5_H_I NXP_S32_PINMUX(0, 0, 181, 0, 85, 6) 885 #define PTF22_EMIOS_1_CH6_H_O NXP_S32_PINMUX(0, 0, 182, 3, 0, 0) 886 #define PTF22_EMIOS_1_CH6_H_I NXP_S32_PINMUX(0, 0, 182, 0, 86, 5) 887 #define PTF23_EMIOS_1_CH7_H_O NXP_S32_PINMUX(0, 0, 183, 3, 0, 0) 888 #define PTF23_EMIOS_1_CH7_H_I NXP_S32_PINMUX(0, 0, 183, 0, 87, 5) 889 #define PTF24_EMIOS_1_CH8_X_O NXP_S32_PINMUX(0, 0, 184, 3, 0, 0) 890 #define PTF24_EMIOS_1_CH8_X_I NXP_S32_PINMUX(0, 0, 184, 0, 88, 3) 891 #define PTF25_EMIOS_1_CH9_H_O NXP_S32_PINMUX(0, 0, 185, 3, 0, 0) 892 #define PTF25_EMIOS_1_CH9_H_I NXP_S32_PINMUX(0, 0, 185, 0, 89, 3) 893 #define PTF26_EMIOS_1_CH10_H_O NXP_S32_PINMUX(0, 0, 186, 3, 0, 0) 894 #define PTF26_EMIOS_1_CH10_H_I NXP_S32_PINMUX(0, 0, 186, 0, 90, 4) 895 #define PTF27_EMIOS_1_CH11_H_O NXP_S32_PINMUX(0, 0, 187, 3, 0, 0) 896 #define PTF27_EMIOS_1_CH11_H_I NXP_S32_PINMUX(0, 0, 187, 0, 91, 3) 897 #define PTF28_EMIOS_1_CH12_H_O NXP_S32_PINMUX(0, 0, 188, 3, 0, 0) 898 #define PTF28_EMIOS_1_CH12_H_I NXP_S32_PINMUX(0, 0, 188, 0, 92, 4) 899 #define PTF29_EMIOS_1_CH13_H_O NXP_S32_PINMUX(0, 0, 189, 3, 0, 0) 900 #define PTF29_EMIOS_1_CH13_H_I NXP_S32_PINMUX(0, 0, 189, 0, 93, 3) 901 #define PTF30_EMIOS_1_CH14_H_O NXP_S32_PINMUX(0, 0, 190, 3, 0, 0) 902 #define PTF30_EMIOS_1_CH14_H_I NXP_S32_PINMUX(0, 0, 190, 0, 94, 3) 903 #define PTF31_EMIOS_1_CH15_H_O NXP_S32_PINMUX(0, 0, 191, 3, 0, 0) 904 #define PTF31_EMIOS_1_CH15_H_I NXP_S32_PINMUX(0, 0, 191, 0, 95, 4) 905 #define PTG0_EMIOS_1_CH16_X_O NXP_S32_PINMUX(0, 0, 192, 3, 0, 0) 906 #define PTG0_EMIOS_1_CH16_X_I NXP_S32_PINMUX(0, 0, 192, 0, 96, 4) 907 #define PTG1_EMIOS_1_CH17_Y_O NXP_S32_PINMUX(0, 0, 193, 3, 0, 0) 908 #define PTG1_EMIOS_1_CH17_Y_I NXP_S32_PINMUX(0, 0, 193, 0, 97, 3) 909 #define PTG2_EMIOS_1_CH18_Y_O NXP_S32_PINMUX(0, 0, 194, 3, 0, 0) 910 #define PTG2_EMIOS_1_CH18_Y_I NXP_S32_PINMUX(0, 0, 194, 0, 98, 3) 911 #define PTG3_EMIOS_1_CH19_Y_O NXP_S32_PINMUX(0, 0, 195, 3, 0, 0) 912 #define PTG3_EMIOS_1_CH19_Y_I NXP_S32_PINMUX(0, 0, 195, 0, 99, 3) 913 #define PTG4_EMIOS_1_CH20_Y_O NXP_S32_PINMUX(0, 0, 196, 3, 0, 0) 914 #define PTG4_EMIOS_1_CH20_Y_I NXP_S32_PINMUX(0, 0, 196, 0, 100, 3) 915 #define PTG5_EMIOS_1_CH21_Y_O NXP_S32_PINMUX(0, 0, 197, 3, 0, 0) 916 #define PTG5_EMIOS_1_CH21_Y_I NXP_S32_PINMUX(0, 0, 197, 0, 101, 3) 917 #define PTG6_EMIOS_1_CH22_X_O NXP_S32_PINMUX(0, 0, 198, 3, 0, 0) 918 #define PTG6_EMIOS_1_CH22_X_I NXP_S32_PINMUX(0, 0, 198, 0, 102, 3) 919 #define PTG7_EMIOS_1_CH23_X_O NXP_S32_PINMUX(0, 0, 199, 3, 0, 0) 920 #define PTG7_EMIOS_1_CH23_X_I NXP_S32_PINMUX(0, 0, 199, 0, 103, 3) 921 922 /* LPSPI0 */ 923 #define PTA0_LPSPI0_PCS7_O NXP_S32_PINMUX(0, 0, 0, 6, 0, 0) 924 #define PTA0_LPSPI0_PCS7_I NXP_S32_PINMUX(0, 0, 0, 0, 228, 1) 925 #define PTA1_LPSPI0_PCS6_O NXP_S32_PINMUX(0, 0, 1, 6, 0, 0) 926 #define PTA1_LPSPI0_PCS6_I NXP_S32_PINMUX(0, 0, 1, 0, 227, 1) 927 #define PTA7_LPSPI0_PCS1_O NXP_S32_PINMUX(0, 0, 7, 2, 0, 0) 928 #define PTA7_LPSPI0_PCS1_I NXP_S32_PINMUX(0, 0, 7, 0, 222, 3) 929 #define PTA15_LPSPI0_PCS3_O NXP_S32_PINMUX(0, 0, 15, 3, 0, 0) 930 #define PTA15_LPSPI0_PCS3_I NXP_S32_PINMUX(0, 0, 15, 0, 224, 1) 931 #define PTA16_LPSPI0_PCS4_O NXP_S32_PINMUX(0, 0, 16, 4, 0, 0) 932 #define PTA16_LPSPI0_PCS4_I NXP_S32_PINMUX(0, 0, 16, 0, 225, 1) 933 #define PTA26_LPSPI0_PCS0_O NXP_S32_PINMUX(0, 0, 26, 4, 0, 0) 934 #define PTA26_LPSPI0_PCS0_I NXP_S32_PINMUX(0, 0, 26, 0, 221, 3) 935 #define PTA30_LPSPI0_SOUT_O NXP_S32_PINMUX(0, 0, 30, 4, 0, 0) 936 #define PTA30_LPSPI0_SOUT_I NXP_S32_PINMUX(0, 0, 30, 0, 231, 4) 937 #define PTA31_LPSPI0_PCS1_O NXP_S32_PINMUX(0, 0, 31, 4, 0, 0) 938 #define PTA31_LPSPI0_PCS1_I NXP_S32_PINMUX(0, 0, 31, 0, 222, 2) 939 #define PTB0_LPSPI0_PCS0_O NXP_S32_PINMUX(0, 0, 32, 3, 0, 0) 940 #define PTB0_LPSPI0_PCS0_I NXP_S32_PINMUX(0, 0, 32, 0, 221, 1) 941 #define PTB1_LPSPI0_SOUT_O NXP_S32_PINMUX(0, 0, 33, 3, 0, 0) 942 #define PTB1_LPSPI0_SOUT_I NXP_S32_PINMUX(0, 0, 33, 0, 231, 3) 943 #define PTB4_LPSPI0_SOUT_O NXP_S32_PINMUX(0, 0, 36, 3, 0, 0) 944 #define PTB4_LPSPI0_SOUT_I NXP_S32_PINMUX(0, 0, 36, 0, 231, 2) 945 #define PTB5_LPSPI0_PCS1_O NXP_S32_PINMUX(0, 0, 37, 3, 0, 0) 946 #define PTB5_LPSPI0_PCS0_O NXP_S32_PINMUX(0, 0, 37, 4, 0, 0) 947 #define PTB5_LPSPI0_PCS0_I NXP_S32_PINMUX(0, 0, 37, 0, 221, 2) 948 #define PTB5_LPSPI0_PCS1_I NXP_S32_PINMUX(0, 0, 37, 0, 222, 1) 949 #define PTB8_LPSPI0_PCS5_O NXP_S32_PINMUX(0, 0, 40, 6, 0, 0) 950 #define PTB8_LPSPI0_PCS5_I NXP_S32_PINMUX(0, 0, 40, 0, 226, 1) 951 #define PTC2_LPSPI0_PCS2_O NXP_S32_PINMUX(0, 0, 66, 4, 0, 0) 952 #define PTC2_LPSPI0_PCS2_I NXP_S32_PINMUX(0, 0, 66, 0, 223, 2) 953 #define PTC6_LPSPI0_PCS1_O NXP_S32_PINMUX(0, 0, 70, 6, 0, 0) 954 #define PTC6_LPSPI0_PCS1_I NXP_S32_PINMUX(0, 0, 70, 0, 222, 4) 955 #define PTC7_LPSPI0_PCS0_O NXP_S32_PINMUX(0, 0, 71, 6, 0, 0) 956 #define PTC7_LPSPI0_PCS0_I NXP_S32_PINMUX(0, 0, 71, 0, 221, 6) 957 #define PTC8_LPSPI0_SCK_O NXP_S32_PINMUX(0, 0, 72, 6, 0, 0) 958 #define PTC8_LPSPI0_SCK_I NXP_S32_PINMUX(0, 0, 72, 0, 229, 1) 959 #define PTC9_LPSPI0_SIN_O NXP_S32_PINMUX(0, 0, 73, 6, 0, 0) 960 #define PTC9_LPSPI0_SIN_I NXP_S32_PINMUX(0, 0, 73, 0, 230, 2) 961 #define PTD5_LPSPI0_PCS1_O NXP_S32_PINMUX(0, 0, 101, 7, 0, 0) 962 #define PTD5_LPSPI0_PCS1_I NXP_S32_PINMUX(0, 0, 101, 0, 222, 5) 963 #define PTD6_LPSPI0_PCS0_O NXP_S32_PINMUX(0, 0, 102, 7, 0, 0) 964 #define PTD6_LPSPI0_PCS0_I NXP_S32_PINMUX(0, 0, 102, 0, 221, 7) 965 #define PTD7_LPSPI0_PCS3_O NXP_S32_PINMUX(0, 0, 103, 4, 0, 0) 966 #define PTD7_LPSPI0_PCS3_I NXP_S32_PINMUX(0, 0, 103, 0, 224, 2) 967 #define PTD10_LPSPI0_SIN_O NXP_S32_PINMUX(0, 0, 106, 5, 0, 0) 968 #define PTD10_LPSPI0_SIN_I NXP_S32_PINMUX(0, 0, 106, 0, 230, 4) 969 #define PTD11_LPSPI0_SCK_O NXP_S32_PINMUX(0, 0, 107, 6, 0, 0) 970 #define PTD11_LPSPI0_SCK_I NXP_S32_PINMUX(0, 0, 107, 0, 229, 5) 971 #define PTD12_LPSPI0_SOUT_O NXP_S32_PINMUX(0, 0, 108, 6, 0, 0) 972 #define PTD12_LPSPI0_SOUT_I NXP_S32_PINMUX(0, 0, 108, 0, 231, 5) 973 #define PTD15_LPSPI0_SCK_O NXP_S32_PINMUX(0, 0, 111, 4, 0, 0) 974 #define PTD15_LPSPI0_SCK_I NXP_S32_PINMUX(0, 0, 111, 0, 229, 3) 975 #define PTD16_LPSPI0_SIN_O NXP_S32_PINMUX(0, 0, 112, 4, 0, 0) 976 #define PTD16_LPSPI0_SIN_I NXP_S32_PINMUX(0, 0, 112, 0, 230, 3) 977 #define PTE0_LPSPI0_SIN_O NXP_S32_PINMUX(0, 0, 128, 2, 0, 0) 978 #define PTE0_LPSPI0_SIN_I NXP_S32_PINMUX(0, 0, 128, 0, 230, 1) 979 #define PTE1_LPSPI0_SCK_O NXP_S32_PINMUX(0, 0, 129, 2, 0, 0) 980 #define PTE1_LPSPI0_SCK_I NXP_S32_PINMUX(0, 0, 129, 0, 229, 2) 981 #define PTE2_LPSPI0_SOUT_O NXP_S32_PINMUX(0, 0, 130, 2, 0, 0) 982 #define PTE2_LPSPI0_SOUT_I NXP_S32_PINMUX(0, 0, 130, 0, 231, 1) 983 #define PTE4_LPSPI0_PCS0_O NXP_S32_PINMUX(0, 0, 132, 1, 0, 0) 984 #define PTE4_LPSPI0_PCS0_I NXP_S32_PINMUX(0, 0, 132, 0, 221, 5) 985 #define PTE6_LPSPI0_PCS2_O NXP_S32_PINMUX(0, 0, 134, 2, 0, 0) 986 #define PTE6_LPSPI0_PCS2_I NXP_S32_PINMUX(0, 0, 134, 0, 223, 1) 987 #define PTF28_LPSPI0_PCS0_O NXP_S32_PINMUX(0, 0, 188, 5, 0, 0) 988 #define PTF28_LPSPI0_PCS0_I NXP_S32_PINMUX(0, 0, 188, 0, 221, 4) 989 990 /* TRGMUX */ 991 #define PTA0_TRGMUX_OUT3 NXP_S32_PINMUX(0, 0, 0, 7, 0, 0) 992 #define PTA1_TRGMUX_OUT0 NXP_S32_PINMUX(0, 0, 1, 7, 0, 0) 993 #define PTA18_TRGMUX_IN12 NXP_S32_PINMUX(0, 0, 18, 0, 356, 1) 994 #define PTA19_TRGMUX_IN13 NXP_S32_PINMUX(0, 0, 19, 0, 357, 1) 995 #define PTA20_TRGMUX_IN14 NXP_S32_PINMUX(0, 0, 20, 0, 358, 1) 996 #define PTA21_TRGMUX_IN15 NXP_S32_PINMUX(0, 0, 21, 0, 359, 1) 997 #define PTA31_TRGMUX_OUT8 NXP_S32_PINMUX(0, 0, 31, 7, 0, 0) 998 #define PTB2_TRGMUX_IN3 NXP_S32_PINMUX(0, 0, 34, 0, 347, 1) 999 #define PTB3_TRGMUX_IN2 NXP_S32_PINMUX(0, 0, 35, 0, 346, 1) 1000 #define PTB4_TRGMUX_IN1 NXP_S32_PINMUX(0, 0, 36, 0, 345, 1) 1001 #define PTB5_TRGMUX_IN0 NXP_S32_PINMUX(0, 0, 37, 0, 344, 1) 1002 #define PTB18_TRGMUX_OUT9 NXP_S32_PINMUX(0, 0, 50, 7, 0, 0) 1003 #define PTB19_TRGMUX_OUT10 NXP_S32_PINMUX(0, 0, 51, 7, 0, 0) 1004 #define PTB20_TRGMUX_OUT11 NXP_S32_PINMUX(0, 0, 52, 7, 0, 0) 1005 #define PTB21_TRGMUX_OUT12 NXP_S32_PINMUX(0, 0, 53, 7, 0, 0) 1006 #define PTB22_TRGMUX_OUT13 NXP_S32_PINMUX(0, 0, 54, 7, 0, 0) 1007 #define PTB23_TRGMUX_OUT14 NXP_S32_PINMUX(0, 0, 55, 7, 0, 0) 1008 #define PTC10_TRGMUX_IN11 NXP_S32_PINMUX(0, 0, 74, 0, 355, 1) 1009 #define PTC11_TRGMUX_IN10 NXP_S32_PINMUX(0, 0, 75, 0, 354, 1) 1010 #define PTC14_TRGMUX_IN9 NXP_S32_PINMUX(0, 0, 78, 0, 353, 1) 1011 #define PTC15_TRGMUX_IN8 NXP_S32_PINMUX(0, 0, 79, 0, 352, 1) 1012 #define PTC24_TRGMUX_OUT15 NXP_S32_PINMUX(0, 0, 88, 7, 0, 0) 1013 #define PTD0_TRGMUX_OUT1 NXP_S32_PINMUX(0, 0, 96, 7, 0, 0) 1014 #define PTD1_TRGMUX_OUT2 NXP_S32_PINMUX(0, 0, 97, 7, 0, 0) 1015 #define PTD2_TRGMUX_IN5 NXP_S32_PINMUX(0, 0, 98, 0, 349, 1) 1016 #define PTD3_TRGMUX_IN4 NXP_S32_PINMUX(0, 0, 99, 0, 348, 1) 1017 #define PTD5_TRGMUX_IN7 NXP_S32_PINMUX(0, 0, 101, 0, 351, 1) 1018 #define PTE3_TRGMUX_IN6 NXP_S32_PINMUX(0, 0, 131, 0, 350, 1) 1019 #define PTE10_TRGMUX_OUT4 NXP_S32_PINMUX(0, 0, 138, 7, 0, 0) 1020 #define PTE11_TRGMUX_OUT5 NXP_S32_PINMUX(0, 0, 139, 7, 0, 0) 1021 #define PTE15_TRGMUX_OUT6 NXP_S32_PINMUX(0, 0, 143, 7, 0, 0) 1022 #define PTE16_TRGMUX_OUT7 NXP_S32_PINMUX(0, 0, 144, 7, 0, 0) 1023 1024 /* LPUART0 */ 1025 #define PTA0_LPUART0_CTS NXP_S32_PINMUX(0, 0, 0, 0, 360, 1) 1026 #define PTA1_LPUART0_RTS NXP_S32_PINMUX(0, 0, 1, 3, 0, 0) 1027 #define PTA2_LPUART0_RX NXP_S32_PINMUX(0, 0, 2, 0, 187, 1) 1028 #define PTA3_LPUART0_TX_O NXP_S32_PINMUX(0, 0, 3, 6, 0, 0) 1029 #define PTA3_LPUART0_TX_I NXP_S32_PINMUX(0, 0, 3, 0, 363, 1) 1030 #define PTA27_LPUART0_TX_O NXP_S32_PINMUX(0, 0, 27, 4, 0, 0) 1031 #define PTA27_LPUART0_TX_I NXP_S32_PINMUX(0, 0, 27, 0, 363, 4) 1032 #define PTA28_LPUART0_RX NXP_S32_PINMUX(0, 0, 28, 0, 187, 4) 1033 #define PTB0_LPUART0_RX NXP_S32_PINMUX(0, 0, 32, 0, 187, 2) 1034 #define PTB1_LPUART0_TX_O NXP_S32_PINMUX(0, 0, 33, 2, 0, 0) 1035 #define PTB1_LPUART0_TX_I NXP_S32_PINMUX(0, 0, 33, 0, 363, 2) 1036 #define PTC2_LPUART0_RX NXP_S32_PINMUX(0, 0, 66, 0, 187, 3) 1037 #define PTC3_LPUART0_TX_O NXP_S32_PINMUX(0, 0, 67, 4, 0, 0) 1038 #define PTC3_LPUART0_TX_I NXP_S32_PINMUX(0, 0, 67, 0, 363, 3) 1039 #define PTC8_LPUART0_CTS NXP_S32_PINMUX(0, 0, 72, 0, 360, 2) 1040 #define PTC9_LPUART0_RTS NXP_S32_PINMUX(0, 0, 73, 3, 0, 0) 1041 1042 /* FCCU */ 1043 #define PTA2_FCCU_ERR0 NXP_S32_PINMUX(0, 0, 2, 1, 0, 0) 1044 #define PTA2_FCCU_ERR_IN0 NXP_S32_PINMUX(0, 0, 2, 0, 148, 1) 1045 #define PTA3_FCCU_ERR1 NXP_S32_PINMUX(0, 0, 3, 1, 0, 0) 1046 #define PTA3_FCCU_ERR_IN1 NXP_S32_PINMUX(0, 0, 3, 0, 149, 1) 1047 #define PTE15_FCCU_ERR0 NXP_S32_PINMUX(0, 0, 143, 1, 0, 0) 1048 #define PTE15_FCCU_ERR_IN0 NXP_S32_PINMUX(0, 0, 143, 0, 148, 2) 1049 #define PTE16_FCCU_ERR1 NXP_S32_PINMUX(0, 0, 144, 1, 0, 0) 1050 #define PTE16_FCCU_ERR_IN1 NXP_S32_PINMUX(0, 0, 144, 0, 149, 2) 1051 #define PTF14_FCCU_ERR0 NXP_S32_PINMUX(0, 0, 174, 4, 0, 0) 1052 #define PTF14_FCCU_ERR_IN0 NXP_S32_PINMUX(0, 0, 174, 0, 148, 3) 1053 #define PTF15_FCCU_ERR1 NXP_S32_PINMUX(0, 0, 175, 5, 0, 0) 1054 #define PTF15_FCCU_ERR_IN1 NXP_S32_PINMUX(0, 0, 175, 0, 149, 3) 1055 1056 /* LPSPI5 */ 1057 #define PTA2_LPSPI5_SIN_O NXP_S32_PINMUX(0, 0, 2, 7, 0, 0) 1058 #define PTA2_LPSPI5_SIN_I NXP_S32_PINMUX(0, 0, 2, 0, 267, 2) 1059 #define PTA3_LPSPI5_SCK_O NXP_S32_PINMUX(0, 0, 3, 7, 0, 0) 1060 #define PTA3_LPSPI5_SCK_I NXP_S32_PINMUX(0, 0, 3, 0, 266, 2) 1061 #define PTA14_LPSPI5_PCS1_O NXP_S32_PINMUX(0, 0, 14, 7, 0, 0) 1062 #define PTA14_LPSPI5_PCS1_I NXP_S32_PINMUX(0, 0, 14, 0, 263, 2) 1063 #define PTA15_LPSPI5_PCS0_O NXP_S32_PINMUX(0, 0, 15, 6, 0, 0) 1064 #define PTA15_LPSPI5_PCS0_I NXP_S32_PINMUX(0, 0, 15, 0, 262, 3) 1065 #define PTD2_LPSPI5_SOUT_O NXP_S32_PINMUX(0, 0, 98, 7, 0, 0) 1066 #define PTD2_LPSPI5_SOUT_I NXP_S32_PINMUX(0, 0, 98, 0, 268, 2) 1067 #define PTD4_LPSPI5_PCS0_O NXP_S32_PINMUX(0, 0, 100, 7, 0, 0) 1068 #define PTD4_LPSPI5_PCS0_I NXP_S32_PINMUX(0, 0, 100, 0, 262, 2) 1069 #define PTD13_LPSPI5_SIN_O NXP_S32_PINMUX(0, 0, 109, 1, 0, 0) 1070 #define PTD13_LPSPI5_SIN_I NXP_S32_PINMUX(0, 0, 109, 0, 267, 1) 1071 #define PTD14_LPSPI5_SCK_O NXP_S32_PINMUX(0, 0, 110, 1, 0, 0) 1072 #define PTD14_LPSPI5_SCK_I NXP_S32_PINMUX(0, 0, 110, 0, 266, 1) 1073 #define PTD17_LPSPI5_PCS0_O NXP_S32_PINMUX(0, 0, 113, 1, 0, 0) 1074 #define PTD17_LPSPI5_PCS0_I NXP_S32_PINMUX(0, 0, 113, 0, 262, 1) 1075 #define PTD26_LPSPI5_SCK_O NXP_S32_PINMUX(0, 0, 122, 6, 0, 0) 1076 #define PTD26_LPSPI5_SCK_I NXP_S32_PINMUX(0, 0, 122, 0, 266, 3) 1077 #define PTD27_LPSPI5_SOUT_O NXP_S32_PINMUX(0, 0, 123, 6, 0, 0) 1078 #define PTD27_LPSPI5_SOUT_I NXP_S32_PINMUX(0, 0, 123, 0, 268, 3) 1079 #define PTD28_LPSPI5_SIN_O NXP_S32_PINMUX(0, 0, 124, 6, 0, 0) 1080 #define PTD28_LPSPI5_SIN_I NXP_S32_PINMUX(0, 0, 124, 0, 267, 3) 1081 #define PTD29_LPSPI5_PCS2_O NXP_S32_PINMUX(0, 0, 125, 6, 0, 0) 1082 #define PTD29_LPSPI5_PCS2_I NXP_S32_PINMUX(0, 0, 125, 0, 264, 1) 1083 #define PTD30_LPSPI5_PCS3_O NXP_S32_PINMUX(0, 0, 126, 6, 0, 0) 1084 #define PTD30_LPSPI5_PCS3_I NXP_S32_PINMUX(0, 0, 126, 0, 265, 1) 1085 #define PTE8_LPSPI5_PCS1_O NXP_S32_PINMUX(0, 0, 136, 3, 0, 0) 1086 #define PTE8_LPSPI5_PCS1_I NXP_S32_PINMUX(0, 0, 136, 0, 263, 1) 1087 #define PTE9_LPSPI5_SOUT_O NXP_S32_PINMUX(0, 0, 137, 1, 0, 0) 1088 #define PTE9_LPSPI5_SOUT_I NXP_S32_PINMUX(0, 0, 137, 0, 268, 1) 1089 1090 /* LPSPI1 */ 1091 #define PTA2_LPSPI1_SIN NXP_S32_PINMUX(0, 0, 2, 0, 239, 2) 1092 #define PTA3_LPSPI1_SCK_O NXP_S32_PINMUX(0, 0, 3, 3, 0, 0) 1093 #define PTA3_LPSPI1_SCK_I NXP_S32_PINMUX(0, 0, 3, 0, 238, 1) 1094 #define PTA6_LPSPI1_PCS1_O NXP_S32_PINMUX(0, 0, 6, 3, 0, 0) 1095 #define PTA6_LPSPI1_PCS1_I NXP_S32_PINMUX(0, 0, 6, 0, 233, 1) 1096 #define PTA11_LPSPI1_PCS0_O NXP_S32_PINMUX(0, 0, 11, 6, 0, 0) 1097 #define PTA11_LPSPI1_PCS0_I NXP_S32_PINMUX(0, 0, 11, 0, 232, 2) 1098 #define PTA12_LPSPI1_PCS5_O NXP_S32_PINMUX(0, 0, 12, 1, 0, 0) 1099 #define PTA12_LPSPI1_PCS5_I NXP_S32_PINMUX(0, 0, 12, 0, 237, 1) 1100 #define PTA13_LPSPI1_PCS4_O NXP_S32_PINMUX(0, 0, 13, 1, 0, 0) 1101 #define PTA13_LPSPI1_PCS4_I NXP_S32_PINMUX(0, 0, 13, 0, 236, 1) 1102 #define PTA14_LPSPI1_PCS3_O NXP_S32_PINMUX(0, 0, 14, 3, 0, 0) 1103 #define PTA14_LPSPI1_PCS3_I NXP_S32_PINMUX(0, 0, 14, 0, 235, 2) 1104 #define PTA16_LPSPI1_PCS2_O NXP_S32_PINMUX(0, 0, 16, 3, 0, 0) 1105 #define PTA16_LPSPI1_PCS2_I NXP_S32_PINMUX(0, 0, 16, 0, 234, 2) 1106 #define PTA18_LPSPI1_SOUT_O NXP_S32_PINMUX(0, 0, 18, 4, 0, 0) 1107 #define PTA18_LPSPI1_SOUT_I NXP_S32_PINMUX(0, 0, 18, 0, 240, 4) 1108 #define PTA19_LPSPI1_SCK_O NXP_S32_PINMUX(0, 0, 19, 4, 0, 0) 1109 #define PTA19_LPSPI1_SCK_I NXP_S32_PINMUX(0, 0, 19, 0, 238, 3) 1110 #define PTA20_LPSPI1_SIN_O NXP_S32_PINMUX(0, 0, 20, 4, 0, 0) 1111 #define PTA20_LPSPI1_SIN_I NXP_S32_PINMUX(0, 0, 20, 0, 239, 3) 1112 #define PTA21_LPSPI1_PCS0_O NXP_S32_PINMUX(0, 0, 21, 4, 0, 0) 1113 #define PTA21_LPSPI1_PCS0_I NXP_S32_PINMUX(0, 0, 21, 0, 232, 3) 1114 #define PTA22_LPSPI1_PCS1_O NXP_S32_PINMUX(0, 0, 22, 4, 0, 0) 1115 #define PTA22_LPSPI1_PCS1_I NXP_S32_PINMUX(0, 0, 22, 0, 233, 3) 1116 #define PTA26_LPSPI1_PCS0_O NXP_S32_PINMUX(0, 0, 26, 3, 0, 0) 1117 #define PTA26_LPSPI1_PCS0_I NXP_S32_PINMUX(0, 0, 26, 0, 232, 5) 1118 #define PTA28_LPSPI1_SCK_O NXP_S32_PINMUX(0, 0, 28, 3, 0, 0) 1119 #define PTA28_LPSPI1_SCK_I NXP_S32_PINMUX(0, 0, 28, 0, 238, 4) 1120 #define PTA29_LPSPI1_SIN_O NXP_S32_PINMUX(0, 0, 29, 5, 0, 0) 1121 #define PTA29_LPSPI1_SIN_I NXP_S32_PINMUX(0, 0, 29, 0, 239, 4) 1122 #define PTA30_LPSPI1_SOUT_O NXP_S32_PINMUX(0, 0, 30, 3, 0, 0) 1123 #define PTA30_LPSPI1_SOUT_I NXP_S32_PINMUX(0, 0, 30, 0, 240, 5) 1124 #define PTB14_LPSPI1_SCK_O NXP_S32_PINMUX(0, 0, 46, 3, 0, 0) 1125 #define PTB14_LPSPI1_SCK_I NXP_S32_PINMUX(0, 0, 46, 0, 238, 2) 1126 #define PTB15_LPSPI1_SIN_O NXP_S32_PINMUX(0, 0, 47, 3, 0, 0) 1127 #define PTB15_LPSPI1_SIN_I NXP_S32_PINMUX(0, 0, 47, 0, 239, 1) 1128 #define PTB16_LPSPI1_SOUT_O NXP_S32_PINMUX(0, 0, 48, 3, 0, 0) 1129 #define PTB16_LPSPI1_SOUT_I NXP_S32_PINMUX(0, 0, 48, 0, 240, 2) 1130 #define PTB17_LPSPI1_PCS3_O NXP_S32_PINMUX(0, 0, 49, 3, 0, 0) 1131 #define PTB17_LPSPI1_PCS3_I NXP_S32_PINMUX(0, 0, 49, 0, 235, 1) 1132 #define PTB18_LPSPI1_PCS1_O NXP_S32_PINMUX(0, 0, 50, 4, 0, 0) 1133 #define PTB18_LPSPI1_PCS1_I NXP_S32_PINMUX(0, 0, 50, 0, 233, 2) 1134 #define PTC6_LPSPI1_PCS1_O NXP_S32_PINMUX(0, 0, 70, 3, 0, 0) 1135 #define PTC6_LPSPI1_PCS1_I NXP_S32_PINMUX(0, 0, 70, 0, 233, 4) 1136 #define PTD2_LPSPI1_SOUT_O NXP_S32_PINMUX(0, 0, 98, 3, 0, 0) 1137 #define PTD2_LPSPI1_SOUT_I NXP_S32_PINMUX(0, 0, 98, 0, 240, 1) 1138 #define PTD3_LPSPI1_PCS0_O NXP_S32_PINMUX(0, 0, 99, 3, 0, 0) 1139 #define PTD3_LPSPI1_PCS0_I NXP_S32_PINMUX(0, 0, 99, 0, 232, 1) 1140 #define PTD4_LPSPI1_PCS1_O NXP_S32_PINMUX(0, 0, 100, 3, 0, 0) 1141 #define PTD4_LPSPI1_PCS1_I NXP_S32_PINMUX(0, 0, 100, 0, 233, 6) 1142 #define PTD20_LPSPI1_PCS2_O NXP_S32_PINMUX(0, 0, 116, 5, 0, 0) 1143 #define PTD20_LPSPI1_PCS2_I NXP_S32_PINMUX(0, 0, 116, 0, 234, 1) 1144 #define PTE4_LPSPI1_PCS1_O NXP_S32_PINMUX(0, 0, 132, 2, 0, 0) 1145 #define PTE4_LPSPI1_PCS1_I NXP_S32_PINMUX(0, 0, 132, 0, 233, 5) 1146 #define PTF21_LPSPI1_PCS0_O NXP_S32_PINMUX(0, 0, 181, 5, 0, 0) 1147 #define PTF21_LPSPI1_PCS0_I NXP_S32_PINMUX(0, 0, 181, 0, 232, 4) 1148 1149 /* CMP0 */ 1150 #define PTA4_CMP0_OUT NXP_S32_PINMUX(0, 0, 4, 4, 0, 0) 1151 #define PTA11_CMP0_RRT NXP_S32_PINMUX(0, 0, 11, 5, 0, 0) 1152 #define PTD14_CMP0_RRT NXP_S32_PINMUX(0, 0, 110, 6, 0, 0) 1153 #define PTE3_CMP0_OUT NXP_S32_PINMUX(0, 0, 131, 7, 0, 0) 1154 #define PTF14_CMP0_OUT NXP_S32_PINMUX(0, 0, 174, 3, 0, 0) 1155 #define PTF15_CMP0_RRT NXP_S32_PINMUX(0, 0, 175, 3, 0, 0) 1156 1157 /* JTAG */ 1158 #define PTA4_JTAG_TMSSWD_DIO_O NXP_S32_PINMUX(0, 0, 4, 7, 0, 0) 1159 #define PTA4_JTAG_TMSSWD_DIO_I NXP_S32_PINMUX(0, 0, 4, 0, 186, 0) 1160 #define PTC4_JTAG_TCKSWD_CLK NXP_S32_PINMUX(0, 0, 68, 0, 184, 0) 1161 #define PTC5_JTAG_TDI NXP_S32_PINMUX(0, 0, 69, 0, 185, 0) 1162 1163 /* SYSTEM */ 1164 #define PTA12_CLKOUT_STANDBY NXP_S32_PINMUX(0, 0, 12, 3, 0, 0) 1165 #define PTB5_CLKOUT_RUN NXP_S32_PINMUX(0, 0, 37, 5, 0, 0) 1166 #define PTD10_CLKOUT_RUN NXP_S32_PINMUX(0, 0, 106, 6, 0, 0) 1167 #define PTD14_CLKOUT_RUN NXP_S32_PINMUX(0, 0, 110, 7, 0, 0) 1168 #define PTE10_CLKOUT_STANDBY NXP_S32_PINMUX(0, 0, 138, 5, 0, 0) 1169 1170 /* LPSPI3 */ 1171 #define PTA6_LPSPI3_PCS1_O NXP_S32_PINMUX(0, 0, 6, 6, 0, 0) 1172 #define PTA6_LPSPI3_PCS1_I NXP_S32_PINMUX(0, 0, 6, 0, 249, 5) 1173 #define PTA9_LPSPI3_PCS0_O NXP_S32_PINMUX(0, 0, 9, 6, 0, 0) 1174 #define PTA9_LPSPI3_PCS0_I NXP_S32_PINMUX(0, 0, 9, 0, 248, 3) 1175 #define PTA17_LPSPI3_SOUT_O NXP_S32_PINMUX(0, 0, 17, 6, 0, 0) 1176 #define PTA17_LPSPI3_SOUT_I NXP_S32_PINMUX(0, 0, 17, 0, 254, 2) 1177 #define PTB12_LPSPI3_PCS3_O NXP_S32_PINMUX(0, 0, 44, 1, 0, 0) 1178 #define PTB12_LPSPI3_PCS3_I NXP_S32_PINMUX(0, 0, 44, 0, 251, 1) 1179 #define PTB13_LPSPI3_PCS2_O NXP_S32_PINMUX(0, 0, 45, 1, 0, 0) 1180 #define PTB13_LPSPI3_PCS2_I NXP_S32_PINMUX(0, 0, 45, 0, 250, 1) 1181 #define PTB17_LPSPI3_PCS0_O NXP_S32_PINMUX(0, 0, 49, 6, 0, 0) 1182 #define PTB17_LPSPI3_PCS0_I NXP_S32_PINMUX(0, 0, 49, 0, 248, 2) 1183 #define PTB22_LPSPI3_PCS1_O NXP_S32_PINMUX(0, 0, 54, 3, 0, 0) 1184 #define PTB22_LPSPI3_PCS1_I NXP_S32_PINMUX(0, 0, 54, 0, 249, 4) 1185 #define PTC2_LPSPI3_PCS2_O NXP_S32_PINMUX(0, 0, 66, 3, 0, 0) 1186 #define PTC2_LPSPI3_PCS2_I NXP_S32_PINMUX(0, 0, 66, 0, 250, 4) 1187 #define PTC16_LPSPI3_SIN_O NXP_S32_PINMUX(0, 0, 80, 1, 0, 0) 1188 #define PTC16_LPSPI3_SIN_I NXP_S32_PINMUX(0, 0, 80, 0, 253, 3) 1189 #define PTC17_LPSPI3_SCK_O NXP_S32_PINMUX(0, 0, 81, 1, 0, 0) 1190 #define PTC17_LPSPI3_SCK_I NXP_S32_PINMUX(0, 0, 81, 0, 252, 3) 1191 #define PTD0_LPSPI3_SOUT_O NXP_S32_PINMUX(0, 0, 96, 3, 0, 0) 1192 #define PTD0_LPSPI3_SOUT_I NXP_S32_PINMUX(0, 0, 96, 0, 254, 1) 1193 #define PTD1_LPSPI3_SCK_O NXP_S32_PINMUX(0, 0, 97, 3, 0, 0) 1194 #define PTD1_LPSPI3_SCK_I NXP_S32_PINMUX(0, 0, 97, 0, 252, 1) 1195 #define PTD7_LPSPI3_PCS3_O NXP_S32_PINMUX(0, 0, 103, 3, 0, 0) 1196 #define PTD7_LPSPI3_PCS3_I NXP_S32_PINMUX(0, 0, 103, 0, 251, 5) 1197 #define PTD8_LPSPI3_SOUT_O NXP_S32_PINMUX(0, 0, 104, 1, 0, 0) 1198 #define PTD8_LPSPI3_SOUT_I NXP_S32_PINMUX(0, 0, 104, 0, 254, 3) 1199 #define PTD17_LPSPI3_PCS0_O NXP_S32_PINMUX(0, 0, 113, 5, 0, 0) 1200 #define PTD17_LPSPI3_PCS0_I NXP_S32_PINMUX(0, 0, 113, 0, 248, 1) 1201 #define PTD20_LPSPI3_SIN_O NXP_S32_PINMUX(0, 0, 116, 6, 0, 0) 1202 #define PTD20_LPSPI3_SIN_I NXP_S32_PINMUX(0, 0, 116, 0, 253, 2) 1203 #define PTE7_LPSPI3_SCK_O NXP_S32_PINMUX(0, 0, 135, 6, 0, 0) 1204 #define PTE7_LPSPI3_SCK_I NXP_S32_PINMUX(0, 0, 135, 0, 252, 2) 1205 #define PTE8_LPSPI3_PCS1_O NXP_S32_PINMUX(0, 0, 136, 1, 0, 0) 1206 #define PTE8_LPSPI3_PCS1_I NXP_S32_PINMUX(0, 0, 136, 0, 249, 1) 1207 #define PTE10_LPSPI3_SIN_O NXP_S32_PINMUX(0, 0, 138, 2, 0, 0) 1208 #define PTE10_LPSPI3_SIN_I NXP_S32_PINMUX(0, 0, 138, 0, 253, 1) 1209 #define PTF12_LPSPI3_SIN_O NXP_S32_PINMUX(0, 0, 172, 4, 0, 0) 1210 #define PTF12_LPSPI3_SIN_I NXP_S32_PINMUX(0, 0, 172, 0, 253, 4) 1211 #define PTF13_LPSPI3_SCK_O NXP_S32_PINMUX(0, 0, 173, 4, 0, 0) 1212 #define PTF13_LPSPI3_SCK_I NXP_S32_PINMUX(0, 0, 173, 0, 252, 4) 1213 #define PTF15_LPSPI3_SOUT_O NXP_S32_PINMUX(0, 0, 175, 4, 0, 0) 1214 #define PTF15_LPSPI3_SOUT_I NXP_S32_PINMUX(0, 0, 175, 0, 254, 4) 1215 #define PTF16_LPSPI3_PCS0_O NXP_S32_PINMUX(0, 0, 176, 5, 0, 0) 1216 #define PTF16_LPSPI3_PCS0_I NXP_S32_PINMUX(0, 0, 176, 0, 248, 4) 1217 #define PTF18_LPSPI3_PCS1_O NXP_S32_PINMUX(0, 0, 178, 5, 0, 0) 1218 #define PTF18_LPSPI3_PCS1_I NXP_S32_PINMUX(0, 0, 178, 0, 249, 2) 1219 #define PTF19_LPSPI3_PCS2_O NXP_S32_PINMUX(0, 0, 179, 5, 0, 0) 1220 #define PTF19_LPSPI3_PCS2_I NXP_S32_PINMUX(0, 0, 179, 0, 250, 2) 1221 #define PTF20_LPSPI3_PCS3_O NXP_S32_PINMUX(0, 0, 180, 5, 0, 0) 1222 #define PTF20_LPSPI3_PCS3_I NXP_S32_PINMUX(0, 0, 180, 0, 251, 2) 1223 #define PTF23_LPSPI3_PCS3_O NXP_S32_PINMUX(0, 0, 183, 5, 0, 0) 1224 #define PTF23_LPSPI3_PCS3_I NXP_S32_PINMUX(0, 0, 183, 0, 251, 3) 1225 #define PTF29_LPSPI3_PCS1_O NXP_S32_PINMUX(0, 0, 189, 5, 0, 0) 1226 #define PTF29_LPSPI3_PCS1_I NXP_S32_PINMUX(0, 0, 189, 0, 249, 3) 1227 1228 /* CAN0 */ 1229 #define PTA6_CAN0_RX NXP_S32_PINMUX(0, 0, 6, 0, 0, 2) 1230 #define PTA7_CAN0_TX NXP_S32_PINMUX(0, 0, 7, 4, 0, 0) 1231 #define PTA27_CAN0_TX NXP_S32_PINMUX(0, 0, 27, 5, 0, 0) 1232 #define PTA28_CAN0_RX NXP_S32_PINMUX(0, 0, 28, 0, 0, 4) 1233 #define PTB0_CAN0_RX NXP_S32_PINMUX(0, 0, 32, 0, 0, 3) 1234 #define PTB1_CAN0_TX NXP_S32_PINMUX(0, 0, 33, 5, 0, 0) 1235 #define PTC2_CAN0_RX NXP_S32_PINMUX(0, 0, 66, 0, 0, 1) 1236 #define PTC3_CAN0_TX NXP_S32_PINMUX(0, 0, 67, 3, 0, 0) 1237 #define PTF20_CAN0_TX NXP_S32_PINMUX(0, 0, 180, 6, 0, 0) 1238 #define PTF21_CAN0_RX NXP_S32_PINMUX(0, 0, 181, 0, 0, 5) 1239 1240 /* LPUART3 */ 1241 #define PTA6_LPUART3_RX NXP_S32_PINMUX(0, 0, 6, 0, 190, 2) 1242 #define PTA7_LPUART3_TX_O NXP_S32_PINMUX(0, 0, 7, 1, 0, 0) 1243 #define PTA7_LPUART3_TX_I NXP_S32_PINMUX(0, 0, 7, 0, 366, 1) 1244 #define PTD2_LPUART3_TX_O NXP_S32_PINMUX(0, 0, 98, 6, 0, 0) 1245 #define PTD2_LPUART3_TX_I NXP_S32_PINMUX(0, 0, 98, 0, 366, 2) 1246 #define PTD3_LPUART3_RX NXP_S32_PINMUX(0, 0, 99, 0, 190, 3) 1247 #define PTE15_LPUART3_RX NXP_S32_PINMUX(0, 0, 143, 0, 190, 1) 1248 #define PTE16_LPUART3_TX_O NXP_S32_PINMUX(0, 0, 144, 2, 0, 0) 1249 #define PTE16_LPUART3_TX_I NXP_S32_PINMUX(0, 0, 144, 0, 366, 3) 1250 1251 /* LPUART1 */ 1252 #define PTA6_LPUART1_CTS NXP_S32_PINMUX(0, 0, 6, 0, 361, 2) 1253 #define PTA7_LPUART1_RTS NXP_S32_PINMUX(0, 0, 7, 5, 0, 0) 1254 #define PTA18_LPUART1_TX_O NXP_S32_PINMUX(0, 0, 18, 3, 0, 0) 1255 #define PTA18_LPUART1_TX_I NXP_S32_PINMUX(0, 0, 18, 0, 364, 4) 1256 #define PTA19_LPUART1_RX NXP_S32_PINMUX(0, 0, 19, 0, 188, 5) 1257 #define PTB22_LPUART1_TX_O NXP_S32_PINMUX(0, 0, 54, 5, 0, 0) 1258 #define PTB22_LPUART1_TX_I NXP_S32_PINMUX(0, 0, 54, 0, 364, 5) 1259 #define PTB23_LPUART1_RX NXP_S32_PINMUX(0, 0, 55, 0, 188, 4) 1260 #define PTC6_LPUART1_RX NXP_S32_PINMUX(0, 0, 70, 0, 188, 1) 1261 #define PTC7_LPUART1_TX_O NXP_S32_PINMUX(0, 0, 71, 2, 0, 0) 1262 #define PTC7_LPUART1_TX_I NXP_S32_PINMUX(0, 0, 71, 0, 364, 1) 1263 #define PTC8_LPUART1_RX NXP_S32_PINMUX(0, 0, 72, 0, 188, 2) 1264 #define PTC9_LPUART1_TX_O NXP_S32_PINMUX(0, 0, 73, 2, 0, 0) 1265 #define PTC9_LPUART1_TX_I NXP_S32_PINMUX(0, 0, 73, 0, 364, 2) 1266 #define PTD13_LPUART1_RX NXP_S32_PINMUX(0, 0, 109, 0, 188, 3) 1267 #define PTD14_LPUART1_TX_O NXP_S32_PINMUX(0, 0, 110, 3, 0, 0) 1268 #define PTD14_LPUART1_TX_I NXP_S32_PINMUX(0, 0, 110, 0, 364, 3) 1269 #define PTE2_LPUART1_CTS NXP_S32_PINMUX(0, 0, 130, 0, 361, 1) 1270 #define PTE6_LPUART1_RTS NXP_S32_PINMUX(0, 0, 134, 3, 0, 0) 1271 #define PTE15_LPUART1_CTS NXP_S32_PINMUX(0, 0, 143, 0, 361, 3) 1272 #define PTE16_LPUART1_RTS NXP_S32_PINMUX(0, 0, 144, 5, 0, 0) 1273 1274 /* LPSPI2 */ 1275 #define PTA8_LPSPI2_SOUT_O NXP_S32_PINMUX(0, 0, 8, 3, 0, 0) 1276 #define PTA8_LPSPI2_SOUT_I NXP_S32_PINMUX(0, 0, 8, 0, 247, 1) 1277 #define PTA9_LPSPI2_PCS0_O NXP_S32_PINMUX(0, 0, 9, 3, 0, 0) 1278 #define PTA9_LPSPI2_PCS0_I NXP_S32_PINMUX(0, 0, 9, 0, 241, 1) 1279 #define PTA15_LPSPI2_PCS3_O NXP_S32_PINMUX(0, 0, 15, 4, 0, 0) 1280 #define PTA15_LPSPI2_PCS3_I NXP_S32_PINMUX(0, 0, 15, 0, 244, 1) 1281 #define PTA21_LPSPI2_PCS2_O NXP_S32_PINMUX(0, 0, 21, 1, 0, 0) 1282 #define PTA21_LPSPI2_PCS2_I NXP_S32_PINMUX(0, 0, 21, 0, 243, 1) 1283 #define PTB2_LPSPI2_SIN_O NXP_S32_PINMUX(0, 0, 34, 3, 0, 0) 1284 #define PTB2_LPSPI2_SIN_I NXP_S32_PINMUX(0, 0, 34, 0, 246, 2) 1285 #define PTB3_LPSPI2_SOUT_O NXP_S32_PINMUX(0, 0, 35, 3, 0, 0) 1286 #define PTB3_LPSPI2_SOUT_I NXP_S32_PINMUX(0, 0, 35, 0, 247, 2) 1287 #define PTB25_LPSPI2_PCS0_O NXP_S32_PINMUX(0, 0, 57, 5, 0, 0) 1288 #define PTB25_LPSPI2_PCS0_I NXP_S32_PINMUX(0, 0, 57, 0, 241, 4) 1289 #define PTB27_LPSPI2_SOUT_O NXP_S32_PINMUX(0, 0, 59, 5, 0, 0) 1290 #define PTB27_LPSPI2_SOUT_I NXP_S32_PINMUX(0, 0, 59, 0, 247, 3) 1291 #define PTB28_LPSPI2_SIN_O NXP_S32_PINMUX(0, 0, 60, 5, 0, 0) 1292 #define PTB28_LPSPI2_SIN_I NXP_S32_PINMUX(0, 0, 60, 0, 246, 3) 1293 #define PTB29_LPSPI2_SCK_O NXP_S32_PINMUX(0, 0, 61, 5, 0, 0) 1294 #define PTB29_LPSPI2_SCK_I NXP_S32_PINMUX(0, 0, 61, 0, 245, 3) 1295 #define PTC10_LPSPI2_PCS1_O NXP_S32_PINMUX(0, 0, 74, 4, 0, 0) 1296 #define PTC10_LPSPI2_PCS1_I NXP_S32_PINMUX(0, 0, 74, 0, 242, 3) 1297 #define PTC12_LPSPI2_PCS1_O NXP_S32_PINMUX(0, 0, 76, 4, 0, 0) 1298 #define PTC12_LPSPI2_PCS1_I NXP_S32_PINMUX(0, 0, 76, 0, 242, 4) 1299 #define PTC14_LPSPI2_PCS0_O NXP_S32_PINMUX(0, 0, 78, 3, 0, 0) 1300 #define PTC14_LPSPI2_PCS0_I NXP_S32_PINMUX(0, 0, 78, 0, 241, 2) 1301 #define PTC15_LPSPI2_SCK_O NXP_S32_PINMUX(0, 0, 79, 3, 0, 0) 1302 #define PTC15_LPSPI2_SCK_I NXP_S32_PINMUX(0, 0, 79, 0, 245, 2) 1303 #define PTC19_LPSPI2_PCS1_O NXP_S32_PINMUX(0, 0, 83, 5, 0, 0) 1304 #define PTC19_LPSPI2_PCS1_I NXP_S32_PINMUX(0, 0, 83, 0, 242, 2) 1305 #define PTE10_LPSPI2_PCS1_O NXP_S32_PINMUX(0, 0, 138, 3, 0, 0) 1306 #define PTE10_LPSPI2_PCS1_I NXP_S32_PINMUX(0, 0, 138, 0, 242, 1) 1307 #define PTE11_LPSPI2_PCS0_O NXP_S32_PINMUX(0, 0, 139, 2, 0, 0) 1308 #define PTE11_LPSPI2_PCS0_I NXP_S32_PINMUX(0, 0, 139, 0, 241, 3) 1309 #define PTE13_LPSPI2_PCS2_O NXP_S32_PINMUX(0, 0, 141, 3, 0, 0) 1310 #define PTE13_LPSPI2_PCS0_O NXP_S32_PINMUX(0, 0, 141, 5, 0, 0) 1311 #define PTE13_LPSPI2_PCS0_I NXP_S32_PINMUX(0, 0, 141, 0, 241, 5) 1312 #define PTE13_LPSPI2_PCS2_I NXP_S32_PINMUX(0, 0, 141, 0, 243, 2) 1313 #define PTE15_LPSPI2_SCK_O NXP_S32_PINMUX(0, 0, 143, 3, 0, 0) 1314 #define PTE15_LPSPI2_SCK_I NXP_S32_PINMUX(0, 0, 143, 0, 245, 1) 1315 #define PTE16_LPSPI2_SIN_O NXP_S32_PINMUX(0, 0, 144, 3, 0, 0) 1316 #define PTE16_LPSPI2_SIN_I NXP_S32_PINMUX(0, 0, 144, 0, 246, 1) 1317 #define PTF0_LPSPI2_SCK_O NXP_S32_PINMUX(0, 0, 160, 3, 0, 0) 1318 #define PTF0_LPSPI2_SCK_I NXP_S32_PINMUX(0, 0, 160, 0, 245, 4) 1319 #define PTF1_LPSPI2_SIN_O NXP_S32_PINMUX(0, 0, 161, 3, 0, 0) 1320 #define PTF1_LPSPI2_SIN_I NXP_S32_PINMUX(0, 0, 161, 0, 246, 4) 1321 #define PTF2_LPSPI2_SOUT_O NXP_S32_PINMUX(0, 0, 162, 3, 0, 0) 1322 #define PTF2_LPSPI2_SOUT_I NXP_S32_PINMUX(0, 0, 162, 0, 247, 4) 1323 #define PTF3_LPSPI2_PCS0_O NXP_S32_PINMUX(0, 0, 163, 3, 0, 0) 1324 #define PTF3_LPSPI2_PCS0_I NXP_S32_PINMUX(0, 0, 163, 0, 241, 6) 1325 #define PTF25_LPSPI2_PCS2_O NXP_S32_PINMUX(0, 0, 185, 5, 0, 0) 1326 #define PTF25_LPSPI2_PCS2_I NXP_S32_PINMUX(0, 0, 185, 0, 243, 3) 1327 #define PTF26_LPSPI2_PCS3_O NXP_S32_PINMUX(0, 0, 186, 5, 0, 0) 1328 #define PTF26_LPSPI2_PCS3_I NXP_S32_PINMUX(0, 0, 186, 0, 244, 2) 1329 1330 /* EMIOS_2 */ 1331 #define PTA8_EMIOS_2_CH7_H_O NXP_S32_PINMUX(0, 0, 8, 6, 0, 0) 1332 #define PTA8_EMIOS_2_CH7_H_I NXP_S32_PINMUX(0, 0, 8, 0, 119, 3) 1333 #define PTA14_EMIOS_2_CH18_Y_O NXP_S32_PINMUX(0, 0, 14, 4, 0, 0) 1334 #define PTA14_EMIOS_2_CH18_Y_I NXP_S32_PINMUX(0, 0, 14, 0, 130, 4) 1335 #define PTA18_EMIOS_2_CH0_X_O NXP_S32_PINMUX(0, 0, 18, 6, 0, 0) 1336 #define PTA18_EMIOS_2_CH0_X_I NXP_S32_PINMUX(0, 0, 18, 0, 112, 2) 1337 #define PTA19_EMIOS_2_CH1_H_O NXP_S32_PINMUX(0, 0, 19, 6, 0, 0) 1338 #define PTA19_EMIOS_2_CH1_H_I NXP_S32_PINMUX(0, 0, 19, 0, 113, 2) 1339 #define PTA20_EMIOS_2_CH2_H_O NXP_S32_PINMUX(0, 0, 20, 6, 0, 0) 1340 #define PTA20_EMIOS_2_CH2_H_I NXP_S32_PINMUX(0, 0, 20, 0, 114, 2) 1341 #define PTA21_EMIOS_2_CH3_H_O NXP_S32_PINMUX(0, 0, 21, 6, 0, 0) 1342 #define PTA21_EMIOS_2_CH3_H_I NXP_S32_PINMUX(0, 0, 21, 0, 115, 2) 1343 #define PTA25_EMIOS_2_CH8_X NXP_S32_PINMUX(0, 0, 23, 0, 120, 2) 1344 #define PTA26_EMIOS_2_CH9_H_O NXP_S32_PINMUX(0, 0, 26, 6, 0, 0) 1345 #define PTA26_EMIOS_2_CH9_H_I NXP_S32_PINMUX(0, 0, 26, 0, 121, 2) 1346 #define PTA27_EMIOS_2_CH10_H_O NXP_S32_PINMUX(0, 0, 27, 6, 0, 0) 1347 #define PTA27_EMIOS_2_CH10_H_I NXP_S32_PINMUX(0, 0, 27, 0, 122, 2) 1348 #define PTA28_EMIOS_2_CH11_H_O NXP_S32_PINMUX(0, 0, 28, 6, 0, 0) 1349 #define PTA28_EMIOS_2_CH11_H_I NXP_S32_PINMUX(0, 0, 28, 0, 123, 2) 1350 #define PTA29_EMIOS_2_CH12_H_O NXP_S32_PINMUX(0, 0, 29, 6, 0, 0) 1351 #define PTA29_EMIOS_2_CH12_H_I NXP_S32_PINMUX(0, 0, 29, 0, 124, 1) 1352 #define PTA30_EMIOS_2_CH13_H_O NXP_S32_PINMUX(0, 0, 30, 6, 0, 0) 1353 #define PTA30_EMIOS_2_CH13_H_I NXP_S32_PINMUX(0, 0, 30, 0, 125, 2) 1354 #define PTB18_EMIOS_2_CH14_H_O NXP_S32_PINMUX(0, 0, 50, 5, 0, 0) 1355 #define PTB18_EMIOS_2_CH14_H_I NXP_S32_PINMUX(0, 0, 50, 0, 126, 2) 1356 #define PTB19_EMIOS_2_CH15_H_O NXP_S32_PINMUX(0, 0, 51, 5, 0, 0) 1357 #define PTB19_EMIOS_2_CH15_H_I NXP_S32_PINMUX(0, 0, 51, 0, 127, 3) 1358 #define PTB20_EMIOS_2_CH16_X_O NXP_S32_PINMUX(0, 0, 52, 5, 0, 0) 1359 #define PTB20_EMIOS_2_CH16_X_I NXP_S32_PINMUX(0, 0, 52, 0, 128, 2) 1360 #define PTB21_EMIOS_2_CH17_Y_O NXP_S32_PINMUX(0, 0, 53, 5, 0, 0) 1361 #define PTB21_EMIOS_2_CH17_Y_I NXP_S32_PINMUX(0, 0, 53, 0, 129, 2) 1362 #define PTB22_EMIOS_2_CH18_Y_O NXP_S32_PINMUX(0, 0, 54, 4, 0, 0) 1363 #define PTB22_EMIOS_2_CH18_Y_I NXP_S32_PINMUX(0, 0, 54, 0, 130, 2) 1364 #define PTB23_EMIOS_2_CH19_Y_O NXP_S32_PINMUX(0, 0, 55, 4, 0, 0) 1365 #define PTB23_EMIOS_2_CH19_Y_I NXP_S32_PINMUX(0, 0, 55, 0, 131, 2) 1366 #define PTB24_EMIOS_2_CH20_Y_O NXP_S32_PINMUX(0, 0, 56, 4, 0, 0) 1367 #define PTB24_EMIOS_2_CH20_Y_I NXP_S32_PINMUX(0, 0, 56, 0, 132, 2) 1368 #define PTB25_EMIOS_2_CH21_Y_O NXP_S32_PINMUX(0, 0, 57, 4, 0, 0) 1369 #define PTB25_EMIOS_2_CH21_Y_I NXP_S32_PINMUX(0, 0, 57, 0, 133, 2) 1370 #define PTB26_EMIOS_2_CH22_X_O NXP_S32_PINMUX(0, 0, 58, 4, 0, 0) 1371 #define PTB26_EMIOS_2_CH22_X_I NXP_S32_PINMUX(0, 0, 58, 0, 134, 2) 1372 #define PTB27_EMIOS_2_CH23_X_O NXP_S32_PINMUX(0, 0, 59, 4, 0, 0) 1373 #define PTB27_EMIOS_2_CH23_X_I NXP_S32_PINMUX(0, 0, 59, 0, 135, 2) 1374 #define PTB28_EMIOS_2_CH10_H_O NXP_S32_PINMUX(0, 0, 60, 4, 0, 0) 1375 #define PTB28_EMIOS_2_CH10_H_I NXP_S32_PINMUX(0, 0, 60, 0, 122, 3) 1376 #define PTB29_EMIOS_2_CH11_H_O NXP_S32_PINMUX(0, 0, 61, 4, 0, 0) 1377 #define PTB29_EMIOS_2_CH11_H_I NXP_S32_PINMUX(0, 0, 61, 0, 123, 3) 1378 #define PTC16_EMIOS_2_CH9_H_O NXP_S32_PINMUX(0, 0, 80, 3, 0, 0) 1379 #define PTC16_EMIOS_2_CH9_H_I NXP_S32_PINMUX(0, 0, 80, 0, 121, 4) 1380 #define PTC18_EMIOS_2_CH12_H_O NXP_S32_PINMUX(0, 0, 82, 4, 0, 0) 1381 #define PTC18_EMIOS_2_CH12_H_I NXP_S32_PINMUX(0, 0, 82, 0, 124, 3) 1382 #define PTC19_EMIOS_2_CH13_H_O NXP_S32_PINMUX(0, 0, 83, 4, 0, 0) 1383 #define PTC19_EMIOS_2_CH13_H_I NXP_S32_PINMUX(0, 0, 83, 0, 125, 3) 1384 #define PTC20_EMIOS_2_CH14_H_O NXP_S32_PINMUX(0, 0, 84, 4, 0, 0) 1385 #define PTC20_EMIOS_2_CH14_H_I NXP_S32_PINMUX(0, 0, 84, 0, 126, 3) 1386 #define PTC21_EMIOS_2_CH15_H_O NXP_S32_PINMUX(0, 0, 85, 4, 0, 0) 1387 #define PTC21_EMIOS_2_CH15_H_I NXP_S32_PINMUX(0, 0, 85, 0, 127, 5) 1388 #define PTC24_EMIOS_2_CH0_X_O NXP_S32_PINMUX(0, 0, 88, 4, 0, 0) 1389 #define PTC24_EMIOS_2_CH0_X_I NXP_S32_PINMUX(0, 0, 88, 0, 112, 5) 1390 #define PTC25_EMIOS_2_CH1_H_O NXP_S32_PINMUX(0, 0, 89, 4, 0, 0) 1391 #define PTC25_EMIOS_2_CH1_H_I NXP_S32_PINMUX(0, 0, 89, 0, 113, 3) 1392 #define PTC26_EMIOS_2_CH2_H_O NXP_S32_PINMUX(0, 0, 90, 4, 0, 0) 1393 #define PTC26_EMIOS_2_CH2_H_I NXP_S32_PINMUX(0, 0, 90, 0, 114, 3) 1394 #define PTC27_EMIOS_2_CH3_H_O NXP_S32_PINMUX(0, 0, 91, 4, 0, 0) 1395 #define PTC27_EMIOS_2_CH3_H_I NXP_S32_PINMUX(0, 0, 91, 0, 115, 3) 1396 #define PTC29_EMIOS_2_CH4_H_O NXP_S32_PINMUX(0, 0, 93, 4, 0, 0) 1397 #define PTC29_EMIOS_2_CH4_H_I NXP_S32_PINMUX(0, 0, 93, 0, 116, 2) 1398 #define PTC30_EMIOS_2_CH5_H_O NXP_S32_PINMUX(0, 0, 94, 4, 0, 0) 1399 #define PTC30_EMIOS_2_CH5_H_I NXP_S32_PINMUX(0, 0, 94, 0, 117, 3) 1400 #define PTC31_EMIOS_2_CH6_H_O NXP_S32_PINMUX(0, 0, 95, 5, 0, 0) 1401 #define PTC31_EMIOS_2_CH6_H_I NXP_S32_PINMUX(0, 0, 95, 0, 118, 2) 1402 #define PTD20_EMIOS_2_CH0_X_O NXP_S32_PINMUX(0, 0, 116, 4, 0, 0) 1403 #define PTD20_EMIOS_2_CH0_X_I NXP_S32_PINMUX(0, 0, 116, 0, 112, 3) 1404 #define PTD21_EMIOS_2_CH8_X_O NXP_S32_PINMUX(0, 0, 117, 4, 0, 0) 1405 #define PTD21_EMIOS_2_CH8_X_I NXP_S32_PINMUX(0, 0, 117, 0, 120, 3) 1406 #define PTD22_EMIOS_2_CH22_X_O NXP_S32_PINMUX(0, 0, 118, 4, 0, 0) 1407 #define PTD22_EMIOS_2_CH22_X_I NXP_S32_PINMUX(0, 0, 118, 0, 134, 3) 1408 #define PTD23_EMIOS_2_CH23_X_O NXP_S32_PINMUX(0, 0, 119, 4, 0, 0) 1409 #define PTD23_EMIOS_2_CH23_X_I NXP_S32_PINMUX(0, 0, 119, 0, 135, 3) 1410 #define PTD26_EMIOS_2_CH7_H_O NXP_S32_PINMUX(0, 0, 122, 4, 0, 0) 1411 #define PTD26_EMIOS_2_CH7_H_I NXP_S32_PINMUX(0, 0, 122, 0, 119, 1) 1412 #define PTD27_EMIOS_2_CH9_H_O NXP_S32_PINMUX(0, 0, 123, 4, 0, 0) 1413 #define PTD27_EMIOS_2_CH9_H_I NXP_S32_PINMUX(0, 0, 123, 0, 121, 3) 1414 #define PTD28_EMIOS_2_CH0_X_O NXP_S32_PINMUX(0, 0, 124, 4, 0, 0) 1415 #define PTD28_EMIOS_2_CH0_X_I NXP_S32_PINMUX(0, 0, 124, 0, 112, 4) 1416 #define PTD29_EMIOS_2_CH8_X_O NXP_S32_PINMUX(0, 0, 125, 4, 0, 0) 1417 #define PTD29_EMIOS_2_CH8_X_I NXP_S32_PINMUX(0, 0, 125, 0, 120, 4) 1418 #define PTD30_EMIOS_2_CH16_X_O NXP_S32_PINMUX(0, 0, 126, 4, 0, 0) 1419 #define PTD30_EMIOS_2_CH16_X_I NXP_S32_PINMUX(0, 0, 126, 0, 128, 3) 1420 #define PTD31_EMIOS_2_CH22_X_O NXP_S32_PINMUX(0, 0, 127, 4, 0, 0) 1421 #define PTD31_EMIOS_2_CH22_X_I NXP_S32_PINMUX(0, 0, 127, 0, 134, 4) 1422 #define PTE17_EMIOS_2_CH23_X_O NXP_S32_PINMUX(0, 0, 145, 4, 0, 0) 1423 #define PTE17_EMIOS_2_CH23_X_I NXP_S32_PINMUX(0, 0, 145, 0, 135, 4) 1424 #define PTE18_EMIOS_2_CH17_Y_O NXP_S32_PINMUX(0, 0, 146, 4, 0, 0) 1425 #define PTE18_EMIOS_2_CH17_Y_I NXP_S32_PINMUX(0, 0, 146, 0, 129, 4) 1426 #define PTE21_EMIOS_2_CH19_Y_O NXP_S32_PINMUX(0, 0, 149, 4, 0, 0) 1427 #define PTE21_EMIOS_2_CH19_Y_I NXP_S32_PINMUX(0, 0, 149, 0, 131, 4) 1428 #define PTE22_EMIOS_2_CH20_Y_O NXP_S32_PINMUX(0, 0, 150, 4, 0, 0) 1429 #define PTE22_EMIOS_2_CH20_Y_I NXP_S32_PINMUX(0, 0, 150, 0, 132, 4) 1430 #define PTE23_EMIOS_2_CH21_Y_O NXP_S32_PINMUX(0, 0, 151, 4, 0, 0) 1431 #define PTE23_EMIOS_2_CH21_Y_I NXP_S32_PINMUX(0, 0, 151, 0, 133, 4) 1432 #define PTE24_EMIOS_2_CH4_H_O NXP_S32_PINMUX(0, 0, 152, 4, 0, 0) 1433 #define PTE24_EMIOS_2_CH4_H_I NXP_S32_PINMUX(0, 0, 152, 0, 116, 3) 1434 #define PTE25_EMIOS_2_CH5_H_O NXP_S32_PINMUX(0, 0, 153, 4, 0, 0) 1435 #define PTE25_EMIOS_2_CH5_H_I NXP_S32_PINMUX(0, 0, 153, 0, 117, 2) 1436 #define PTE26_EMIOS_2_CH6_H_O NXP_S32_PINMUX(0, 0, 154, 4, 0, 0) 1437 #define PTE26_EMIOS_2_CH6_H_I NXP_S32_PINMUX(0, 0, 154, 0, 118, 3) 1438 #define PTF0_EMIOS_2_CH0_X_O NXP_S32_PINMUX(0, 0, 160, 2, 0, 0) 1439 #define PTF0_EMIOS_2_CH0_X_I NXP_S32_PINMUX(0, 0, 160, 0, 112, 1) 1440 #define PTF1_EMIOS_2_CH1_H_O NXP_S32_PINMUX(0, 0, 161, 2, 0, 0) 1441 #define PTF1_EMIOS_2_CH1_H_I NXP_S32_PINMUX(0, 0, 161, 0, 113, 1) 1442 #define PTF2_EMIOS_2_CH2_H_O NXP_S32_PINMUX(0, 0, 162, 2, 0, 0) 1443 #define PTF2_EMIOS_2_CH2_H_I NXP_S32_PINMUX(0, 0, 162, 0, 114, 1) 1444 #define PTF3_EMIOS_2_CH3_H_O NXP_S32_PINMUX(0, 0, 163, 2, 0, 0) 1445 #define PTF3_EMIOS_2_CH3_H_I NXP_S32_PINMUX(0, 0, 163, 0, 115, 1) 1446 #define PTF4_EMIOS_2_CH4_H_O NXP_S32_PINMUX(0, 0, 164, 2, 0, 0) 1447 #define PTF4_EMIOS_2_CH4_H_I NXP_S32_PINMUX(0, 0, 164, 0, 116, 1) 1448 #define PTF5_EMIOS_2_CH5_H_O NXP_S32_PINMUX(0, 0, 165, 2, 0, 0) 1449 #define PTF5_EMIOS_2_CH5_H_I NXP_S32_PINMUX(0, 0, 165, 0, 117, 1) 1450 #define PTF6_EMIOS_2_CH6_H_O NXP_S32_PINMUX(0, 0, 166, 2, 0, 0) 1451 #define PTF6_EMIOS_2_CH6_H_I NXP_S32_PINMUX(0, 0, 166, 0, 118, 1) 1452 #define PTF7_EMIOS_2_CH7_H_O NXP_S32_PINMUX(0, 0, 167, 2, 0, 0) 1453 #define PTF7_EMIOS_2_CH7_H_I NXP_S32_PINMUX(0, 0, 167, 0, 119, 2) 1454 #define PTF8_EMIOS_2_CH8_X_O NXP_S32_PINMUX(0, 0, 168, 2, 0, 0) 1455 #define PTF8_EMIOS_2_CH8_X_I NXP_S32_PINMUX(0, 0, 168, 0, 120, 1) 1456 #define PTF9_EMIOS_2_CH9_H_O NXP_S32_PINMUX(0, 0, 169, 2, 0, 0) 1457 #define PTF9_EMIOS_2_CH9_H_I NXP_S32_PINMUX(0, 0, 169, 0, 121, 1) 1458 #define PTF10_EMIOS_2_CH10_H_O NXP_S32_PINMUX(0, 0, 170, 2, 0, 0) 1459 #define PTF10_EMIOS_2_CH10_H_I NXP_S32_PINMUX(0, 0, 170, 0, 122, 1) 1460 #define PTF11_EMIOS_2_CH11_H_O NXP_S32_PINMUX(0, 0, 171, 2, 0, 0) 1461 #define PTF11_EMIOS_2_CH11_H_I NXP_S32_PINMUX(0, 0, 171, 0, 123, 1) 1462 #define PTF12_EMIOS_2_CH12_H_O NXP_S32_PINMUX(0, 0, 172, 2, 0, 0) 1463 #define PTF12_EMIOS_2_CH12_H_I NXP_S32_PINMUX(0, 0, 172, 0, 124, 2) 1464 #define PTF13_EMIOS_2_CH13_H_O NXP_S32_PINMUX(0, 0, 173, 2, 0, 0) 1465 #define PTF13_EMIOS_2_CH13_H_I NXP_S32_PINMUX(0, 0, 173, 0, 125, 1) 1466 #define PTF14_EMIOS_2_CH14_H_O NXP_S32_PINMUX(0, 0, 174, 2, 0, 0) 1467 #define PTF14_EMIOS_2_CH14_H_I NXP_S32_PINMUX(0, 0, 174, 0, 126, 1) 1468 #define PTF15_EMIOS_2_CH15_H_O NXP_S32_PINMUX(0, 0, 175, 2, 0, 0) 1469 #define PTF15_EMIOS_2_CH15_H_I NXP_S32_PINMUX(0, 0, 175, 0, 127, 1) 1470 #define PTF16_EMIOS_2_CH16_X_O NXP_S32_PINMUX(0, 0, 176, 2, 0, 0) 1471 #define PTF16_EMIOS_2_CH16_X_I NXP_S32_PINMUX(0, 0, 176, 0, 128, 4) 1472 #define PTF17_EMIOS_2_CH17_Y_O NXP_S32_PINMUX(0, 0, 177, 2, 0, 0) 1473 #define PTF17_EMIOS_2_CH17_Y_I NXP_S32_PINMUX(0, 0, 177, 0, 129, 3) 1474 #define PTF18_EMIOS_2_CH18_Y_O NXP_S32_PINMUX(0, 0, 178, 2, 0, 0) 1475 #define PTF18_EMIOS_2_CH18_Y_I NXP_S32_PINMUX(0, 0, 178, 0, 130, 3) 1476 #define PTF19_EMIOS_2_CH19_Y_O NXP_S32_PINMUX(0, 0, 179, 2, 0, 0) 1477 #define PTF19_EMIOS_2_CH19_Y_I NXP_S32_PINMUX(0, 0, 179, 0, 131, 3) 1478 #define PTF20_EMIOS_2_CH20_Y_O NXP_S32_PINMUX(0, 0, 180, 2, 0, 0) 1479 #define PTF20_EMIOS_2_CH20_Y_I NXP_S32_PINMUX(0, 0, 180, 0, 132, 3) 1480 #define PTF21_EMIOS_2_CH21_Y_O NXP_S32_PINMUX(0, 0, 181, 2, 0, 0) 1481 #define PTF21_EMIOS_2_CH21_Y_I NXP_S32_PINMUX(0, 0, 181, 0, 133, 3) 1482 #define PTF22_EMIOS_2_CH22_X_O NXP_S32_PINMUX(0, 0, 182, 2, 0, 0) 1483 #define PTF22_EMIOS_2_CH22_X_I NXP_S32_PINMUX(0, 0, 182, 0, 134, 5) 1484 #define PTF23_EMIOS_2_CH23_X_O NXP_S32_PINMUX(0, 0, 183, 2, 0, 0) 1485 #define PTF23_EMIOS_2_CH23_X_I NXP_S32_PINMUX(0, 0, 183, 0, 135, 5) 1486 #define PTG15_EMIOS_2_CH15_H_O NXP_S32_PINMUX(0, 0, 207, 5, 0, 0) 1487 #define PTG15_EMIOS_2_CH15_H_I NXP_S32_PINMUX(0, 0, 207, 0, 127, 4) 1488 #define PTG16_EMIOS_2_CH16_X_O NXP_S32_PINMUX(0, 0, 208, 2, 0, 0) 1489 #define PTG16_EMIOS_2_CH16_X_I NXP_S32_PINMUX(0, 0, 208, 0, 128, 1) 1490 #define PTG17_EMIOS_2_CH17_Y_O NXP_S32_PINMUX(0, 0, 209, 2, 0, 0) 1491 #define PTG17_EMIOS_2_CH17_Y_I NXP_S32_PINMUX(0, 0, 209, 0, 129, 1) 1492 #define PTG18_EMIOS_2_CH18_Y_O NXP_S32_PINMUX(0, 0, 210, 2, 0, 0) 1493 #define PTG18_EMIOS_2_CH18_Y_I NXP_S32_PINMUX(0, 0, 210, 0, 130, 1) 1494 #define PTG19_EMIOS_2_CH19_Y_O NXP_S32_PINMUX(0, 0, 211, 2, 0, 0) 1495 #define PTG19_EMIOS_2_CH19_Y_I NXP_S32_PINMUX(0, 0, 211, 0, 131, 1) 1496 #define PTG20_EMIOS_2_CH20_Y_O NXP_S32_PINMUX(0, 0, 212, 2, 0, 0) 1497 #define PTG20_EMIOS_2_CH20_Y_I NXP_S32_PINMUX(0, 0, 212, 0, 132, 1) 1498 #define PTG21_EMIOS_2_CH21_Y_O NXP_S32_PINMUX(0, 0, 213, 2, 0, 0) 1499 #define PTG21_EMIOS_2_CH21_Y_I NXP_S32_PINMUX(0, 0, 213, 0, 133, 1) 1500 #define PTG22_EMIOS_2_CH22_X_O NXP_S32_PINMUX(0, 0, 214, 2, 0, 0) 1501 #define PTG22_EMIOS_2_CH22_X_I NXP_S32_PINMUX(0, 0, 214, 0, 134, 1) 1502 #define PTG23_EMIOS_2_CH23_X_O NXP_S32_PINMUX(0, 0, 215, 2, 0, 0) 1503 #define PTG23_EMIOS_2_CH23_X_I NXP_S32_PINMUX(0, 0, 215, 0, 135, 1) 1504 1505 /* LPUART2 */ 1506 #define PTA8_LPUART2_RX NXP_S32_PINMUX(0, 0, 8, 0, 189, 3) 1507 #define PTA9_LPUART2_TX_O NXP_S32_PINMUX(0, 0, 9, 2, 0, 0) 1508 #define PTA9_LPUART2_TX_I NXP_S32_PINMUX(0, 0, 9, 0, 365, 1) 1509 #define PTA29_LPUART2_TX_O NXP_S32_PINMUX(0, 0, 29, 4, 0, 0) 1510 #define PTA29_LPUART2_TX_I NXP_S32_PINMUX(0, 0, 29, 0, 365, 5) 1511 #define PTA30_LPUART2_RX NXP_S32_PINMUX(0, 0, 30, 0, 189, 4) 1512 #define PTC15_LPUART2_TX_O NXP_S32_PINMUX(0, 0, 79, 5, 0, 0) 1513 #define PTC15_LPUART2_TX_I NXP_S32_PINMUX(0, 0, 79, 0, 365, 2) 1514 #define PTC16_LPUART2_RX NXP_S32_PINMUX(0, 0, 80, 0, 189, 5) 1515 #define PTD6_LPUART2_RX NXP_S32_PINMUX(0, 0, 102, 0, 189, 1) 1516 #define PTD7_LPUART2_TX_O NXP_S32_PINMUX(0, 0, 103, 2, 0, 0) 1517 #define PTD7_LPUART2_TX_I NXP_S32_PINMUX(0, 0, 103, 0, 365, 3) 1518 #define PTD11_LPUART2_CTS NXP_S32_PINMUX(0, 0, 107, 0, 362, 1) 1519 #define PTD12_LPUART2_RTS NXP_S32_PINMUX(0, 0, 108, 3, 0, 0) 1520 #define PTD15_LPUART2_CTS NXP_S32_PINMUX(0, 0, 111, 0, 362, 2) 1521 #define PTD16_LPUART2_RTS NXP_S32_PINMUX(0, 0, 112, 6, 0, 0) 1522 #define PTD17_LPUART2_RX NXP_S32_PINMUX(0, 0, 113, 0, 189, 2) 1523 #define PTE3_LPUART2_RTS NXP_S32_PINMUX(0, 0, 131, 5, 0, 0) 1524 #define PTE9_LPUART2_CTS NXP_S32_PINMUX(0, 0, 137, 0, 362, 3) 1525 #define PTE12_LPUART2_TX_O NXP_S32_PINMUX(0, 0, 140, 3, 0, 0) 1526 #define PTE12_LPUART2_TX_I NXP_S32_PINMUX(0, 0, 140, 0, 365, 4) 1527 1528 /* CMP2 */ 1529 #define PTA9_CMP2_OUT NXP_S32_PINMUX(0, 0, 9, 7, 0, 0) 1530 #define PTC5_CMP2_RRT NXP_S32_PINMUX(0, 0, 69, 5, 0, 0) 1531 #define PTG4_CMP2_OUT NXP_S32_PINMUX(0, 0, 196, 4, 0, 0) 1532 #define PTG5_CMP2_RRT NXP_S32_PINMUX(0, 0, 197, 4, 0, 0) 1533 1534 /* JTAGTRACENOETM */ 1535 #define PTA10_JTAG_TDOTRACENOETM_SWO NXP_S32_PINMUX(0, 0, 10, 7, 0, 0) 1536 1537 /* CAN1 */ 1538 #define PTA11_CAN1_TX NXP_S32_PINMUX(0, 0, 11, 1, 0, 0) 1539 #define PTA12_CAN1_RX NXP_S32_PINMUX(0, 0, 12, 0, 1, 2) 1540 #define PTA22_CAN1_RX NXP_S32_PINMUX(0, 0, 22, 0, 1, 3) 1541 #define PTA23_CAN1_TX NXP_S32_PINMUX(0, 0, 23, 1, 0, 0) 1542 #define PTB22_CAN1_TX NXP_S32_PINMUX(0, 0, 54, 1, 0, 0) 1543 #define PTB23_CAN1_RX NXP_S32_PINMUX(0, 0, 55, 0, 1, 4) 1544 #define PTC8_CAN1_TX NXP_S32_PINMUX(0, 0, 72, 3, 0, 0) 1545 #define PTC9_CAN1_RX NXP_S32_PINMUX(0, 0, 73, 0, 1, 1) 1546 #define PTF14_CAN1_TX NXP_S32_PINMUX(0, 0, 174, 1, 0, 0) 1547 #define PTF15_CAN1_RX NXP_S32_PINMUX(0, 0, 175, 0, 1, 5) 1548 1549 /* CMP1 */ 1550 #define PTA12_CMP1_OUT NXP_S32_PINMUX(0, 0, 12, 7, 0, 0) 1551 #define PTE15_CMP1_RRT NXP_S32_PINMUX(0, 0, 143, 5, 0, 0) 1552 #define PTE30_CMP1_OUT NXP_S32_PINMUX(0, 0, 158, 2, 0, 0) 1553 #define PTE31_CMP1_RRT NXP_S32_PINMUX(0, 0, 159, 2, 0, 0) 1554 1555 /* LPUART11 */ 1556 #define PTA12_LPUART11_RX NXP_S32_PINMUX(0, 0, 12, 0, 198, 2) 1557 #define PTA13_LPUART11_TX_O NXP_S32_PINMUX(0, 0, 13, 7, 0, 0) 1558 #define PTA13_LPUART11_TX_I NXP_S32_PINMUX(0, 0, 13, 0, 374, 1) 1559 #define PTC10_LPUART11_TX_O NXP_S32_PINMUX(0, 0, 74, 2, 0, 0) 1560 #define PTC10_LPUART11_TX_I NXP_S32_PINMUX(0, 0, 74, 0, 374, 2) 1561 #define PTC11_LPUART11_RX NXP_S32_PINMUX(0, 0, 75, 0, 198, 1) 1562 #define PTF27_LPUART11_TX_O NXP_S32_PINMUX(0, 0, 187, 1, 0, 0) 1563 #define PTF27_LPUART11_TX_I NXP_S32_PINMUX(0, 0, 187, 0, 374, 3) 1564 #define PTF28_LPUART11_RX NXP_S32_PINMUX(0, 0, 188, 0, 198, 3) 1565 1566 /* LPUART6 */ 1567 #define PTA15_LPUART6_RX NXP_S32_PINMUX(0, 0, 15, 0, 193, 2) 1568 #define PTA16_LPUART6_TX_O NXP_S32_PINMUX(0, 0, 16, 5, 0, 0) 1569 #define PTA16_LPUART6_TX_I NXP_S32_PINMUX(0, 0, 16, 0, 369, 1) 1570 #define PTB29_LPUART6_TX_O NXP_S32_PINMUX(0, 0, 61, 1, 0, 0) 1571 #define PTB29_LPUART6_TX_I NXP_S32_PINMUX(0, 0, 61, 0, 369, 3) 1572 #define PTC18_LPUART6_RX NXP_S32_PINMUX(0, 0, 82, 0, 193, 4) 1573 #define PTD8_LPUART6_RX NXP_S32_PINMUX(0, 0, 104, 0, 193, 1) 1574 #define PTD9_LPUART6_TX_O NXP_S32_PINMUX(0, 0, 105, 4, 0, 0) 1575 #define PTD9_LPUART6_TX_I NXP_S32_PINMUX(0, 0, 105, 0, 369, 2) 1576 #define PTF2_LPUART6_TX_O NXP_S32_PINMUX(0, 0, 162, 1, 0, 0) 1577 #define PTF2_LPUART6_TX_I NXP_S32_PINMUX(0, 0, 162, 0, 369, 4) 1578 #define PTF3_LPUART6_RX NXP_S32_PINMUX(0, 0, 163, 0, 193, 3) 1579 1580 /* LPUART4 */ 1581 #define PTA17_LPUART4_TX_O NXP_S32_PINMUX(0, 0, 17, 4, 0, 0) 1582 #define PTA17_LPUART4_TX_I NXP_S32_PINMUX(0, 0, 17, 0, 367, 1) 1583 #define PTB16_LPUART4_TX_O NXP_S32_PINMUX(0, 0, 48, 4, 0, 0) 1584 #define PTB16_LPUART4_TX_I NXP_S32_PINMUX(0, 0, 48, 0, 367, 2) 1585 #define PTB17_LPUART4_RX NXP_S32_PINMUX(0, 0, 49, 0, 191, 3) 1586 #define PTE7_LPUART4_RX NXP_S32_PINMUX(0, 0, 135, 0, 191, 4) 1587 #define PTE10_LPUART4_RX NXP_S32_PINMUX(0, 0, 138, 0, 191, 2) 1588 #define PTE11_LPUART4_TX_O NXP_S32_PINMUX(0, 0, 139, 1, 0, 0) 1589 #define PTE11_LPUART4_TX_I NXP_S32_PINMUX(0, 0, 139, 0, 367, 3) 1590 1591 /* EMAC */ 1592 #define PTA26_EMAC_PPS0_O NXP_S32_PINMUX(0, 0, 26, 7, 0, 0) 1593 #define PTA26_EMAC_PPS0_I NXP_S32_PINMUX(0, 0, 26, 0, 144, 3) 1594 #define PTA27_EMAC_PPS1_O NXP_S32_PINMUX(0, 0, 27, 3, 0, 0) 1595 #define PTA27_EMAC_PPS1_I NXP_S32_PINMUX(0, 0, 27, 0, 145, 3) 1596 #define PTA29_EMAC_PPS2_O NXP_S32_PINMUX(0, 0, 29, 3, 0, 0) 1597 #define PTA29_EMAC_PPS2_I NXP_S32_PINMUX(0, 0, 29, 0, 146, 3) 1598 #define PTB4_EMAC_MII_RMII_TXD1 NXP_S32_PINMUX(0, 0, 36, 1, 0, 0) 1599 #define PTB4_EMAC_MII_RMII_MDIO_O NXP_S32_PINMUX(0, 0, 36, 5, 0, 0) 1600 #define PTB4_EMAC_MII_RMII_MDIO_I NXP_S32_PINMUX(0, 0, 36, 0, 291, 1) 1601 #define PTB5_EMAC_MII_RMII_TXD0 NXP_S32_PINMUX(0, 0, 37, 1, 0, 0) 1602 #define PTB5_EMAC_MII_RMII_MDC NXP_S32_PINMUX(0, 0, 37, 7, 0, 0) 1603 #define PTB22_EMAC_MII_CRS NXP_S32_PINMUX(0, 0, 54, 0, 290, 1) 1604 #define PTB23_EMAC_MII_COL NXP_S32_PINMUX(0, 0, 55, 0, 289, 1) 1605 #define PTB28_EMAC_PPS3_O NXP_S32_PINMUX(0, 0, 60, 7, 0, 0) 1606 #define PTB28_EMAC_PPS3_I NXP_S32_PINMUX(0, 0, 60, 0, 147, 2) 1607 #define PTC0_EMAC_MII_RMII_RXD0 NXP_S32_PINMUX(0, 0, 64, 0, 294, 2) 1608 #define PTC0_EMAC_MII_RMII_RXD1 NXP_S32_PINMUX(0, 0, 64, 0, 295, 1) 1609 #define PTC0_EMAC_MII_RMII_TX_CLK NXP_S32_PINMUX(0, 0, 64, 0, 296, 4) 1610 #define PTC1_EMAC_MII_RMII_RXD0 NXP_S32_PINMUX(0, 0, 65, 0, 294, 1) 1611 #define PTC1_EMAC_MII_RMII_RXD1 NXP_S32_PINMUX(0, 0, 65, 0, 295, 2) 1612 #define PTC1_EMAC_MII_RX_CLK NXP_S32_PINMUX(0, 0, 65, 0, 300, 3) 1613 #define PTC2_EMAC_MII_RMII_TXD1 NXP_S32_PINMUX(0, 0, 66, 1, 0, 0) 1614 #define PTC2_EMAC_MII_RMII_TXD0 NXP_S32_PINMUX(0, 0, 66, 5, 0, 0) 1615 #define PTC14_EMAC_MII_COL NXP_S32_PINMUX(0, 0, 78, 0, 289, 2) 1616 #define PTC14_EMAC_MII_RMII_RX_ER NXP_S32_PINMUX(0, 0, 78, 0, 293, 2) 1617 #define PTC14_EMAC_MII_RXD3 NXP_S32_PINMUX(0, 0, 78, 0, 302, 2) 1618 #define PTC15_EMAC_MII_CRS NXP_S32_PINMUX(0, 0, 79, 0, 290, 2) 1619 #define PTC15_EMAC_MII_RMII_RX_DV NXP_S32_PINMUX(0, 0, 79, 0, 292, 2) 1620 #define PTC15_EMAC_MII_RXD2 NXP_S32_PINMUX(0, 0, 79, 0, 301, 2) 1621 #define PTC16_EMAC_MII_RMII_RX_ER NXP_S32_PINMUX(0, 0, 80, 0, 293, 1) 1622 #define PTC17_EMAC_MII_RMII_RX_DV NXP_S32_PINMUX(0, 0, 81, 0, 292, 1) 1623 #define PTD5_EMAC_MII_TXD2 NXP_S32_PINMUX(0, 0, 101, 1, 0, 0) 1624 #define PTD5_EMAC_MII_TXD3 NXP_S32_PINMUX(0, 0, 101, 5, 0, 0) 1625 #define PTD5_EMAC_MII_RX_CLK NXP_S32_PINMUX(0, 0, 101, 0, 300, 2) 1626 #define PTD6_EMAC_MII_TXD3 NXP_S32_PINMUX(0, 0, 102, 1, 0, 0) 1627 #define PTD6_EMAC_MII_TXD2 NXP_S32_PINMUX(0, 0, 102, 5, 0, 0) 1628 #define PTD6_EMAC_MII_RMII_TX_CLK NXP_S32_PINMUX(0, 0, 102, 0, 296, 2) 1629 #define PTD7_EMAC_MII_RMII_TXD0 NXP_S32_PINMUX(0, 0, 103, 1, 0, 0) 1630 #define PTD7_EMAC_MII_RMII_TXD1 NXP_S32_PINMUX(0, 0, 103, 5, 0, 0) 1631 #define PTD8_EMAC_MII_RMII_RXD1 NXP_S32_PINMUX(0, 0, 104, 0, 295, 3) 1632 #define PTD8_EMAC_MII_RXD3 NXP_S32_PINMUX(0, 0, 104, 0, 302, 1) 1633 #define PTD9_EMAC_MII_RMII_RXD0 NXP_S32_PINMUX(0, 0, 105, 0, 294, 3) 1634 #define PTD9_EMAC_MII_RXD2 NXP_S32_PINMUX(0, 0, 105, 0, 301, 1) 1635 #define PTD10_EMAC_MII_TXD3 NXP_S32_PINMUX(0, 0, 106, 1, 0, 0) 1636 #define PTD10_EMAC_MII_RX_CLK NXP_S32_PINMUX(0, 0, 106, 0, 300, 1) 1637 #define PTD11_EMAC_MII_TXD2 NXP_S32_PINMUX(0, 0, 107, 1, 0, 0) 1638 #define PTD11_EMAC_MII_RMII_TX_EN NXP_S32_PINMUX(0, 0, 107, 3, 0, 0) 1639 #define PTD11_EMAC_MII_RMII_TX_CLK NXP_S32_PINMUX(0, 0, 107, 0, 296, 1) 1640 #define PTD12_EMAC_MII_RMII_TX_EN NXP_S32_PINMUX(0, 0, 108, 5, 0, 0) 1641 #define PTD12_EMAC_MII_RMII_TX_CLK NXP_S32_PINMUX(0, 0, 108, 0, 296, 3) 1642 #define PTD13_EMAC_PPS1_O NXP_S32_PINMUX(0, 0, 109, 5, 0, 0) 1643 #define PTD13_EMAC_PPS1_I NXP_S32_PINMUX(0, 0, 109, 0, 145, 2) 1644 #define PTD14_EMAC_PPS0_O NXP_S32_PINMUX(0, 0, 110, 5, 0, 0) 1645 #define PTD14_EMAC_PPS0_I NXP_S32_PINMUX(0, 0, 110, 0, 144, 2) 1646 #define PTD15_EMAC_PPS2_O NXP_S32_PINMUX(0, 0, 111, 5, 0, 0) 1647 #define PTD15_EMAC_PPS2_I NXP_S32_PINMUX(0, 0, 111, 0, 146, 2) 1648 #define PTD16_EMAC_MII_RMII_MDIO_O NXP_S32_PINMUX(0, 0, 112, 3, 0, 0) 1649 #define PTD16_EMAC_MII_RMII_MDIO_I NXP_S32_PINMUX(0, 0, 112, 0, 291, 2) 1650 #define PTD17_EMAC_MII_RMII_MDC NXP_S32_PINMUX(0, 0, 113, 3, 0, 0) 1651 #define PTD17_EMAC_PPS2_O NXP_S32_PINMUX(0, 0, 113, 7, 0, 0) 1652 #define PTD17_EMAC_PPS2_I NXP_S32_PINMUX(0, 0, 113, 0, 146, 1) 1653 #define PTE3_EMAC_PPS0_O NXP_S32_PINMUX(0, 0, 131, 6, 0, 0) 1654 #define PTE3_EMAC_PPS0_I NXP_S32_PINMUX(0, 0, 131, 0, 144, 1) 1655 #define PTE8_EMAC_MII_RMII_MDC NXP_S32_PINMUX(0, 0, 136, 5, 0, 0) 1656 #define PTE9_EMAC_PPS3_O NXP_S32_PINMUX(0, 0, 137, 5, 0, 0) 1657 #define PTE9_EMAC_MII_RMII_TX_EN NXP_S32_PINMUX(0, 0, 137, 6, 0, 0) 1658 #define PTE9_EMAC_PPS3_I NXP_S32_PINMUX(0, 0, 137, 0, 147, 1) 1659 #define PTE12_EMAC_PPS3_O NXP_S32_PINMUX(0, 0, 140, 5, 0, 0) 1660 #define PTE12_EMAC_PPS3_I NXP_S32_PINMUX(0, 0, 140, 0, 147, 3) 1661 #define PTE14_EMAC_PPS1_O NXP_S32_PINMUX(0, 0, 142, 7, 0, 0) 1662 #define PTE14_EMAC_PPS1_I NXP_S32_PINMUX(0, 0, 142, 0, 145, 1) 1663 1664 /* LPI2C0 */ 1665 #define PTB0_LPI2C0_SDAS_O NXP_S32_PINMUX(0, 0, 32, 1, 0, 0) 1666 #define PTB0_LPI2C0_SDAS_I NXP_S32_PINMUX(0, 0, 32, 0, 215, 1) 1667 #define PTB1_LPI2C0_SCLS_O NXP_S32_PINMUX(0, 0, 33, 1, 0, 0) 1668 #define PTB1_LPI2C0_SCLS_I NXP_S32_PINMUX(0, 0, 33, 0, 213, 1) 1669 #define PTB11_LPI2C0_HREQ NXP_S32_PINMUX(0, 0, 43, 0, 211, 1) 1670 #define PTC7_LPI2C0_HREQ NXP_S32_PINMUX(0, 0, 71, 0, 211, 2) 1671 #define PTC8_LPI2C0_SCL_O NXP_S32_PINMUX(0, 0, 72, 1, 0, 0) 1672 #define PTC8_LPI2C0_SCL_I NXP_S32_PINMUX(0, 0, 72, 0, 212, 1) 1673 #define PTC9_LPI2C0_SDA_O NXP_S32_PINMUX(0, 0, 73, 1, 0, 0) 1674 #define PTC9_LPI2C0_SDA_I NXP_S32_PINMUX(0, 0, 73, 0, 214, 1) 1675 #define PTD13_LPI2C0_SDA_O NXP_S32_PINMUX(0, 0, 109, 4, 0, 0) 1676 #define PTD13_LPI2C0_SDA_I NXP_S32_PINMUX(0, 0, 109, 0, 214, 2) 1677 #define PTD14_LPI2C0_SCL_O NXP_S32_PINMUX(0, 0, 110, 4, 0, 0) 1678 #define PTD14_LPI2C0_SCL_I NXP_S32_PINMUX(0, 0, 110, 0, 212, 2) 1679 #define PTF20_LPI2C0_SCL_O NXP_S32_PINMUX(0, 0, 180, 4, 0, 0) 1680 #define PTF20_LPI2C0_SCL_I NXP_S32_PINMUX(0, 0, 180, 0, 212, 3) 1681 #define PTF21_LPI2C0_SDA_O NXP_S32_PINMUX(0, 0, 181, 4, 0, 0) 1682 #define PTF21_LPI2C0_SDA_I NXP_S32_PINMUX(0, 0, 181, 0, 214, 3) 1683 1684 /* LCU1 */ 1685 #define PTB0_LCU1_OUT5 NXP_S32_PINMUX(0, 0, 32, 5, 0, 0) 1686 #define PTB1_LCU1_OUT4 NXP_S32_PINMUX(0, 0, 33, 7, 0, 0) 1687 #define PTB2_LCU1_OUT3 NXP_S32_PINMUX(0, 0, 34, 5, 0, 0) 1688 #define PTB3_LCU1_OUT2 NXP_S32_PINMUX(0, 0, 35, 6, 0, 0) 1689 #define PTB28_LCU1_OUT11 NXP_S32_PINMUX(0, 0, 60, 6, 0, 0) 1690 #define PTB29_LCU1_OUT10 NXP_S32_PINMUX(0, 0, 61, 6, 0, 0) 1691 #define PTC8_LCU1_OUT7 NXP_S32_PINMUX(0, 0, 72, 5, 0, 0) 1692 #define PTC9_LCU1_OUT6 NXP_S32_PINMUX(0, 0, 73, 5, 0, 0) 1693 #define PTC10_LCU1_OUT11 NXP_S32_PINMUX(0, 0, 74, 6, 0, 0) 1694 #define PTC11_LCU1_OUT10 NXP_S32_PINMUX(0, 0, 75, 7, 0, 0) 1695 #define PTC12_LCU1_OUT9 NXP_S32_PINMUX(0, 0, 76, 6, 0, 0) 1696 #define PTC13_LCU1_OUT8 NXP_S32_PINMUX(0, 0, 77, 6, 0, 0) 1697 #define PTC14_LCU1_OUT1 NXP_S32_PINMUX(0, 0, 78, 6, 0, 0) 1698 #define PTC15_LCU1_OUT0 NXP_S32_PINMUX(0, 0, 79, 6, 0, 0) 1699 #define PTC18_LCU1_OUT7 NXP_S32_PINMUX(0, 0, 82, 6, 0, 0) 1700 #define PTC19_LCU1_OUT6 NXP_S32_PINMUX(0, 0, 83, 6, 0, 0) 1701 #define PTC20_LCU1_OUT5 NXP_S32_PINMUX(0, 0, 84, 6, 0, 0) 1702 #define PTC21_LCU1_OUT4 NXP_S32_PINMUX(0, 0, 85, 6, 0, 0) 1703 #define PTC23_LCU1_OUT0 NXP_S32_PINMUX(0, 0, 87, 6, 0, 0) 1704 #define PTC24_LCU1_OUT1 NXP_S32_PINMUX(0, 0, 88, 6, 0, 0) 1705 #define PTC25_LCU1_OUT2 NXP_S32_PINMUX(0, 0, 89, 6, 0, 0) 1706 #define PTC26_LCU1_OUT9 NXP_S32_PINMUX(0, 0, 90, 6, 0, 0) 1707 #define PTC27_LCU1_OUT3 NXP_S32_PINMUX(0, 0, 91, 6, 0, 0) 1708 #define PTC28_LCU1_OUT8 NXP_S32_PINMUX(0, 0, 92, 6, 0, 0) 1709 1710 /* HSE */ 1711 #define PTB0_HSE_TAMPER_LOOP_OUT0 NXP_S32_PINMUX(0, 0, 32, 7, 0, 0) 1712 #define PTB1_HSE_TAMPER_EXTIN0 NXP_S32_PINMUX(0, 0, 33, 0, 343, 1) 1713 #define PTB30_HSE_TAMPER_LOOP_OUT0 NXP_S32_PINMUX(0, 0, 62, 5, 0, 0) 1714 #define PTB31_HSE_TAMPER_EXTIN0 NXP_S32_PINMUX(0, 0, 63, 0, 343, 3) 1715 #define PTD23_HSE_TAMPER_LOOP_OUT0 NXP_S32_PINMUX(0, 0, 119, 5, 0, 0) 1716 #define PTD24_HSE_TAMPER_EXTIN0 NXP_S32_PINMUX(0, 0, 120, 0, 343, 2) 1717 #define PTF11_HSE_TAMPER_EXTIN0 NXP_S32_PINMUX(0, 0, 171, 0, 343, 4) 1718 #define PTF19_HSE_TAMPER_LOOP_OUT0 NXP_S32_PINMUX(0, 0, 179, 6, 0, 0) 1719 1720 /* ADC1 */ 1721 #define PTB2_ADC1_MA0 NXP_S32_PINMUX(0, 0, 34, 1, 0, 0) 1722 #define PTB23_ADC1_MA0 NXP_S32_PINMUX(0, 0, 55, 1, 0, 0) 1723 #define PTB24_ADC1_MA1 NXP_S32_PINMUX(0, 0, 56, 1, 0, 0) 1724 #define PTB28_ADC1_MA2 NXP_S32_PINMUX(0, 0, 60, 1, 0, 0) 1725 #define PTC12_ADC1_MA2 NXP_S32_PINMUX(0, 0, 76, 1, 0, 0) 1726 #define PTC13_ADC1_MA1 NXP_S32_PINMUX(0, 0, 77, 4, 0, 0) 1727 #define PTC20_ADC1_MA2 NXP_S32_PINMUX(0, 0, 84, 5, 0, 0) 1728 #define PTC21_ADC1_MA1 NXP_S32_PINMUX(0, 0, 85, 5, 0, 0) 1729 #define PTC27_ADC1_MA0 NXP_S32_PINMUX(0, 0, 91, 5, 0, 0) 1730 #define PTF16_ADC1_MA0 NXP_S32_PINMUX(0, 0, 176, 4, 0, 0) 1731 #define PTF17_ADC1_MA1 NXP_S32_PINMUX(0, 0, 177, 4, 0, 0) 1732 #define PTF18_ADC1_MA2 NXP_S32_PINMUX(0, 0, 178, 4, 0, 0) 1733 #define PTF29_ADC1_MA0 NXP_S32_PINMUX(0, 0, 189, 4, 0, 0) 1734 #define PTF30_ADC1_MA1 NXP_S32_PINMUX(0, 0, 190, 4, 0, 0) 1735 #define PTF31_ADC1_MA2 NXP_S32_PINMUX(0, 0, 191, 1, 0, 0) 1736 1737 /* SAI0 */ 1738 #define PTB2_SAI0_D0_O NXP_S32_PINMUX(0, 0, 34, 6, 0, 0) 1739 #define PTB2_SAI0_D0_I NXP_S32_PINMUX(0, 0, 34, 0, 316, 1) 1740 #define PTB3_SAI0_MCLK NXP_S32_PINMUX(0, 0, 35, 0, 320, 1) 1741 #define PTB29_SAI0_D1_O NXP_S32_PINMUX(0, 0, 61, 7, 0, 0) 1742 #define PTB29_SAI0_D1_I NXP_S32_PINMUX(0, 0, 61, 0, 317, 1) 1743 #define PTC12_SAI0_BCLK_O NXP_S32_PINMUX(0, 0, 76, 7, 0, 0) 1744 #define PTC12_SAI0_BCLK_I NXP_S32_PINMUX(0, 0, 76, 0, 315, 1) 1745 #define PTC13_SAI0_SYNC_O NXP_S32_PINMUX(0, 0, 77, 7, 0, 0) 1746 #define PTC13_SAI0_SYNC_I NXP_S32_PINMUX(0, 0, 77, 0, 321, 1) 1747 #define PTC18_SAI0_D2_O NXP_S32_PINMUX(0, 0, 82, 7, 0, 0) 1748 #define PTC18_SAI0_D2_I NXP_S32_PINMUX(0, 0, 82, 0, 318, 1) 1749 #define PTC19_SAI0_D3_O NXP_S32_PINMUX(0, 0, 83, 7, 0, 0) 1750 #define PTC19_SAI0_D3_I NXP_S32_PINMUX(0, 0, 83, 0, 319, 1) 1751 1752 /* CAN4 */ 1753 #define PTB2_CAN4_RX NXP_S32_PINMUX(0, 0, 34, 0, 4, 2) 1754 #define PTB3_CAN4_TX NXP_S32_PINMUX(0, 0, 35, 5, 0, 0) 1755 #define PTC30_CAN4_TX NXP_S32_PINMUX(0, 0, 94, 1, 0, 0) 1756 #define PTC31_CAN4_RX NXP_S32_PINMUX(0, 0, 95, 0, 4, 3) 1757 #define PTE3_CAN4_TX NXP_S32_PINMUX(0, 0, 131, 1, 0, 0) 1758 #define PTE14_CAN4_RX NXP_S32_PINMUX(0, 0, 142, 0, 4, 1) 1759 #define PTE30_CAN4_TX NXP_S32_PINMUX(0, 0, 158, 1, 0, 0) 1760 #define PTE31_CAN4_RX NXP_S32_PINMUX(0, 0, 159, 0, 4, 4) 1761 #define PTG8_CAN4_TX NXP_S32_PINMUX(0, 0, 200, 1, 0, 0) 1762 #define PTG9_CAN4_RX NXP_S32_PINMUX(0, 0, 201, 0, 4, 5) 1763 1764 /* LPUART9 */ 1765 #define PTB2_LPUART9_RX NXP_S32_PINMUX(0, 0, 34, 0, 196, 2) 1766 #define PTB3_LPUART9_TX_O NXP_S32_PINMUX(0, 0, 35, 1, 0, 0) 1767 #define PTB3_LPUART9_TX_I NXP_S32_PINMUX(0, 0, 35, 0, 372, 1) 1768 #define PTB9_LPUART9_RX NXP_S32_PINMUX(0, 0, 41, 0, 196, 1) 1769 #define PTB10_LPUART9_TX_O NXP_S32_PINMUX(0, 0, 42, 5, 0, 0) 1770 #define PTB10_LPUART9_TX_I NXP_S32_PINMUX(0, 0, 42, 0, 372, 2) 1771 #define PTF23_LPUART9_TX_O NXP_S32_PINMUX(0, 0, 183, 1, 0, 0) 1772 #define PTF23_LPUART9_TX_I NXP_S32_PINMUX(0, 0, 183, 0, 372, 3) 1773 #define PTF24_LPUART9_RX NXP_S32_PINMUX(0, 0, 184, 0, 196, 3) 1774 1775 /* ADC0 */ 1776 #define PTB3_ADC0_MA0 NXP_S32_PINMUX(0, 0, 35, 4, 0, 0) 1777 #define PTC6_ADC0_MA2 NXP_S32_PINMUX(0, 0, 70, 7, 0, 0) 1778 #define PTC14_ADC0_MA1 NXP_S32_PINMUX(0, 0, 78, 4, 0, 0) 1779 #define PTC15_ADC0_MA2 NXP_S32_PINMUX(0, 0, 79, 4, 0, 0) 1780 #define PTE2_ADC0_MA0 NXP_S32_PINMUX(0, 0, 130, 7, 0, 0) 1781 #define PTE6_ADC0_MA1 NXP_S32_PINMUX(0, 0, 134, 7, 0, 0) 1782 #define PTF9_ADC0_MA0 NXP_S32_PINMUX(0, 0, 169, 3, 0, 0) 1783 #define PTF10_ADC0_MA1 NXP_S32_PINMUX(0, 0, 170, 3, 0, 0) 1784 #define PTF11_ADC0_MA2 NXP_S32_PINMUX(0, 0, 171, 3, 0, 0) 1785 #define PTF12_ADC0_MA0 NXP_S32_PINMUX(0, 0, 172, 3, 0, 0) 1786 #define PTF13_ADC0_MA1 NXP_S32_PINMUX(0, 0, 173, 3, 0, 0) 1787 #define PTF19_ADC0_MA2 NXP_S32_PINMUX(0, 0, 179, 4, 0, 0) 1788 1789 /* LPUART8 */ 1790 #define PTB12_LPUART8_RX NXP_S32_PINMUX(0, 0, 44, 0, 195, 1) 1791 #define PTB13_LPUART8_TX_O NXP_S32_PINMUX(0, 0, 45, 6, 0, 0) 1792 #define PTB13_LPUART8_TX_I NXP_S32_PINMUX(0, 0, 45, 0, 371, 1) 1793 #define PTD15_LPUART8_RX NXP_S32_PINMUX(0, 0, 111, 0, 195, 2) 1794 #define PTD16_LPUART8_TX_O NXP_S32_PINMUX(0, 0, 112, 7, 0, 0) 1795 #define PTD16_LPUART8_TX_I NXP_S32_PINMUX(0, 0, 112, 0, 371, 2) 1796 #define PTF20_LPUART8_TX_O NXP_S32_PINMUX(0, 0, 180, 1, 0, 0) 1797 #define PTF20_LPUART8_TX_I NXP_S32_PINMUX(0, 0, 180, 0, 371, 3) 1798 #define PTF21_LPUART8_RX NXP_S32_PINMUX(0, 0, 181, 0, 195, 3) 1799 1800 /* LPUART7 */ 1801 #define PTB14_LPUART7_RX NXP_S32_PINMUX(0, 0, 46, 0, 194, 1) 1802 #define PTB15_LPUART7_TX_O NXP_S32_PINMUX(0, 0, 47, 6, 0, 0) 1803 #define PTB15_LPUART7_TX_I NXP_S32_PINMUX(0, 0, 47, 0, 370, 1) 1804 #define PTC19_LPUART7_TX_O NXP_S32_PINMUX(0, 0, 83, 1, 0, 0) 1805 #define PTC19_LPUART7_TX_I NXP_S32_PINMUX(0, 0, 83, 0, 370, 2) 1806 #define PTC20_LPUART7_RX NXP_S32_PINMUX(0, 0, 84, 0, 194, 4) 1807 #define PTE0_LPUART7_RX NXP_S32_PINMUX(0, 0, 128, 0, 194, 2) 1808 #define PTE1_LPUART7_TX_O NXP_S32_PINMUX(0, 0, 129, 6, 0, 0) 1809 #define PTE1_LPUART7_TX_I NXP_S32_PINMUX(0, 0, 129, 0, 370, 3) 1810 #define PTF18_LPUART7_TX_O NXP_S32_PINMUX(0, 0, 178, 1, 0, 0) 1811 #define PTF18_LPUART7_TX_I NXP_S32_PINMUX(0, 0, 178, 0, 370, 4) 1812 #define PTF19_LPUART7_RX NXP_S32_PINMUX(0, 0, 179, 0, 194, 3) 1813 1814 /* LPUART13 */ 1815 #define PTB18_LPUART13_TX_O NXP_S32_PINMUX(0, 0, 50, 1, 0, 0) 1816 #define PTB18_LPUART13_TX_I NXP_S32_PINMUX(0, 0, 50, 0, 376, 1) 1817 #define PTB19_LPUART13_RX NXP_S32_PINMUX(0, 0, 51, 0, 200, 1) 1818 #define PTC26_LPUART13_TX_O NXP_S32_PINMUX(0, 0, 90, 1, 0, 0) 1819 #define PTC26_LPUART13_TX_I NXP_S32_PINMUX(0, 0, 90, 0, 376, 2) 1820 #define PTC27_LPUART13_RX NXP_S32_PINMUX(0, 0, 91, 0, 200, 2) 1821 #define PTG0_LPUART13_TX_O NXP_S32_PINMUX(0, 0, 192, 1, 0, 0) 1822 #define PTG0_LPUART13_TX_I NXP_S32_PINMUX(0, 0, 192, 0, 376, 3) 1823 #define PTG1_LPUART13_RX NXP_S32_PINMUX(0, 0, 193, 0, 200, 3) 1824 1825 /* LPUART14 */ 1826 #define PTB20_LPUART14_TX_O NXP_S32_PINMUX(0, 0, 52, 1, 0, 0) 1827 #define PTB20_LPUART14_TX_I NXP_S32_PINMUX(0, 0, 52, 0, 377, 1) 1828 #define PTB21_LPUART14_RX NXP_S32_PINMUX(0, 0, 53, 0, 201, 1) 1829 #define PTD26_LPUART14_TX_O NXP_S32_PINMUX(0, 0, 122, 1, 0, 0) 1830 #define PTD26_LPUART14_TX_I NXP_S32_PINMUX(0, 0, 122, 0, 377, 2) 1831 #define PTD27_LPUART14_RX NXP_S32_PINMUX(0, 0, 123, 0, 201, 2) 1832 #define PTG2_LPUART14_TX_O NXP_S32_PINMUX(0, 0, 194, 1, 0, 0) 1833 #define PTG2_LPUART14_TX_I NXP_S32_PINMUX(0, 0, 194, 0, 377, 3) 1834 #define PTG3_LPUART14_RX NXP_S32_PINMUX(0, 0, 195, 0, 201, 3) 1835 1836 /* LPUART15 */ 1837 #define PTB25_LPUART15_TX_O NXP_S32_PINMUX(0, 0, 57, 1, 0, 0) 1838 #define PTB25_LPUART15_TX_I NXP_S32_PINMUX(0, 0, 57, 0, 378, 1) 1839 #define PTB26_LPUART15_RX NXP_S32_PINMUX(0, 0, 58, 0, 202, 1) 1840 #define PTD28_LPUART15_TX_O NXP_S32_PINMUX(0, 0, 124, 1, 0, 0) 1841 #define PTD28_LPUART15_TX_I NXP_S32_PINMUX(0, 0, 124, 0, 378, 2) 1842 #define PTD29_LPUART15_RX NXP_S32_PINMUX(0, 0, 125, 0, 202, 2) 1843 #define PTG4_LPUART15_TX_O NXP_S32_PINMUX(0, 0, 196, 1, 0, 0) 1844 #define PTG4_LPUART15_TX_I NXP_S32_PINMUX(0, 0, 196, 0, 378, 3) 1845 #define PTG5_LPUART15_RX NXP_S32_PINMUX(0, 0, 197, 0, 202, 3) 1846 1847 /* LPUART5 */ 1848 #define PTB27_LPUART5_TX_O NXP_S32_PINMUX(0, 0, 59, 1, 0, 0) 1849 #define PTB27_LPUART5_TX_I NXP_S32_PINMUX(0, 0, 59, 0, 368, 3) 1850 #define PTB28_LPUART5_RX NXP_S32_PINMUX(0, 0, 60, 0, 192, 4) 1851 #define PTD0_LPUART5_RX NXP_S32_PINMUX(0, 0, 96, 0, 192, 2) 1852 #define PTD1_LPUART5_TX_O NXP_S32_PINMUX(0, 0, 97, 1, 0, 0) 1853 #define PTD1_LPUART5_TX_I NXP_S32_PINMUX(0, 0, 97, 0, 368, 1) 1854 #define PTE3_LPUART5_RX NXP_S32_PINMUX(0, 0, 131, 0, 192, 1) 1855 #define PTE14_LPUART5_TX_O NXP_S32_PINMUX(0, 0, 142, 4, 0, 0) 1856 #define PTE14_LPUART5_TX_I NXP_S32_PINMUX(0, 0, 142, 0, 368, 2) 1857 #define PTF0_LPUART5_TX_O NXP_S32_PINMUX(0, 0, 160, 1, 0, 0) 1858 #define PTF0_LPUART5_TX_I NXP_S32_PINMUX(0, 0, 160, 0, 368, 4) 1859 #define PTF1_LPUART5_RX NXP_S32_PINMUX(0, 0, 161, 0, 192, 3) 1860 1861 /* CAN3 */ 1862 #define PTC0_CAN3_TX NXP_S32_PINMUX(0, 0, 64, 1, 0, 0) 1863 #define PTC1_CAN3_RX NXP_S32_PINMUX(0, 0, 65, 0, 3, 2) 1864 #define PTC28_CAN3_TX NXP_S32_PINMUX(0, 0, 92, 1, 0, 0) 1865 #define PTC29_CAN3_RX NXP_S32_PINMUX(0, 0, 93, 0, 3, 3) 1866 #define PTD15_CAN3_RX NXP_S32_PINMUX(0, 0, 111, 0, 3, 1) 1867 #define PTE9_CAN3_TX NXP_S32_PINMUX(0, 0, 137, 4, 0, 0) 1868 #define PTE28_CAN3_TX NXP_S32_PINMUX(0, 0, 156, 1, 0, 0) 1869 #define PTE29_CAN3_RX NXP_S32_PINMUX(0, 0, 157, 0, 3, 4) 1870 #define PTF29_CAN3_TX NXP_S32_PINMUX(0, 0, 189, 1, 0, 0) 1871 #define PTF30_CAN3_RX NXP_S32_PINMUX(0, 0, 190, 0, 3, 5) 1872 1873 /* TRACE */ 1874 #define PTC2_TRACE_ETM_CLKOUT NXP_S32_PINMUX(0, 0, 66, 6, 0, 0) 1875 #define PTD7_TRACE_ETM_D0 NXP_S32_PINMUX(0, 0, 103, 6, 0, 0) 1876 #define PTD10_TRACE_ETM_D3 NXP_S32_PINMUX(0, 0, 106, 4, 0, 0) 1877 #define PTD11_TRACE_ETM_D2 NXP_S32_PINMUX(0, 0, 107, 4, 0, 0) 1878 #define PTD12_TRACE_ETM_D1 NXP_S32_PINMUX(0, 0, 108, 4, 0, 0) 1879 #define PTF28_TRACE_ETM_D5 NXP_S32_PINMUX(0, 0, 188, 7, 0, 0) 1880 #define PTF31_TRACE_ETM_D3 NXP_S32_PINMUX(0, 0, 191, 7, 0, 0) 1881 #define PTG6_TRACE_ETM_CLKOUT NXP_S32_PINMUX(0, 0, 198, 7, 0, 0) 1882 #define PTG7_TRACE_ETM_D0 NXP_S32_PINMUX(0, 0, 199, 7, 0, 0) 1883 #define PTG15_TRACE_ETM_D1 NXP_S32_PINMUX(0, 0, 207, 7, 0, 0) 1884 #define PTG16_TRACE_ETM_D2 NXP_S32_PINMUX(0, 0, 208, 7, 0, 0) 1885 #define PTG17_TRACE_ETM_D4 NXP_S32_PINMUX(0, 0, 209, 7, 0, 0) 1886 #define PTG18_TRACE_ETM_D6 NXP_S32_PINMUX(0, 0, 210, 7, 0, 0) 1887 #define PTG19_TRACE_ETM_D7 NXP_S32_PINMUX(0, 0, 211, 7, 0, 0) 1888 #define PTG20_TRACE_ETM_D8 NXP_S32_PINMUX(0, 0, 212, 7, 0, 0) 1889 #define PTG21_TRACE_ETM_D9 NXP_S32_PINMUX(0, 0, 213, 7, 0, 0) 1890 #define PTG22_TRACE_ETM_D10 NXP_S32_PINMUX(0, 0, 214, 7, 0, 0) 1891 #define PTG23_TRACE_ETM_D11 NXP_S32_PINMUX(0, 0, 215, 7, 0, 0) 1892 #define PTG24_TRACE_ETM_D12 NXP_S32_PINMUX(0, 0, 216, 7, 0, 0) 1893 #define PTG25_TRACE_ETM_D13 NXP_S32_PINMUX(0, 0, 217, 7, 0, 0) 1894 #define PTG26_TRACE_ETM_D14 NXP_S32_PINMUX(0, 0, 218, 7, 0, 0) 1895 #define PTG27_TRACE_ETM_D15 NXP_S32_PINMUX(0, 0, 219, 7, 0, 0) 1896 1897 /* QUADSPI */ 1898 #define PTC2_QUADSPI_IOFA3_O NXP_S32_PINMUX(0, 0, 66, 7, 0, 0) 1899 #define PTC2_QUADSPI_IOFA3_I NXP_S32_PINMUX(0, 0, 66, 0, 308, 1) 1900 #define PTC3_QUADSPI_PCSFA NXP_S32_PINMUX(0, 0, 67, 6, 0, 0) 1901 #define PTD7_QUADSPI_IOFA1_O NXP_S32_PINMUX(0, 0, 103, 7, 0, 0) 1902 #define PTD7_QUADSPI_IOFA1_I NXP_S32_PINMUX(0, 0, 103, 0, 306, 1) 1903 #define PTD10_QUADSPI_SCKFA_O NXP_S32_PINMUX(0, 0, 106, 7, 0, 0) 1904 #define PTD10_QUADSPI_SCKFA_I NXP_S32_PINMUX(0, 0, 106, 0, 309, 1) 1905 #define PTD11_QUADSPI_IOFA0_O NXP_S32_PINMUX(0, 0, 107, 7, 0, 0) 1906 #define PTD11_QUADSPI_IOFA0_I NXP_S32_PINMUX(0, 0, 107, 0, 305, 1) 1907 #define PTD12_QUADSPI_IOFA2_O NXP_S32_PINMUX(0, 0, 108, 7, 0, 0) 1908 #define PTD12_QUADSPI_IOFA2_I NXP_S32_PINMUX(0, 0, 108, 0, 307, 1) 1909 1910 /* LPI2C1 */ 1911 #define PTC5_LPI2C1_HREQ NXP_S32_PINMUX(0, 0, 69, 0, 216, 2) 1912 #define PTC6_LPI2C1_SDA_O NXP_S32_PINMUX(0, 0, 70, 1, 0, 0) 1913 #define PTC6_LPI2C1_SDA_I NXP_S32_PINMUX(0, 0, 70, 0, 219, 2) 1914 #define PTC7_LPI2C1_SCL_O NXP_S32_PINMUX(0, 0, 71, 3, 0, 0) 1915 #define PTC7_LPI2C1_SCL_I NXP_S32_PINMUX(0, 0, 71, 0, 217, 1) 1916 #define PTC15_LPI2C1_SCL_O NXP_S32_PINMUX(0, 0, 79, 7, 0, 0) 1917 #define PTC15_LPI2C1_SCL_I NXP_S32_PINMUX(0, 0, 79, 0, 217, 6) 1918 #define PTC16_LPI2C1_SDAS_O NXP_S32_PINMUX(0, 0, 80, 4, 0, 0) 1919 #define PTC16_LPI2C1_SDA_O NXP_S32_PINMUX(0, 0, 80, 7, 0, 0) 1920 #define PTC16_LPI2C1_SDA_I NXP_S32_PINMUX(0, 0, 80, 0, 219, 5) 1921 #define PTC16_LPI2C1_SDAS_I NXP_S32_PINMUX(0, 0, 80, 0, 220, 1) 1922 #define PTC17_LPI2C1_SCLS_O NXP_S32_PINMUX(0, 0, 81, 4, 0, 0) 1923 #define PTC17_LPI2C1_SCLS_I NXP_S32_PINMUX(0, 0, 81, 0, 218, 2) 1924 #define PTC28_LPI2C1_SCL_O NXP_S32_PINMUX(0, 0, 92, 5, 0, 0) 1925 #define PTC28_LPI2C1_SCL_I NXP_S32_PINMUX(0, 0, 92, 0, 217, 4) 1926 #define PTC29_LPI2C1_SDA_O NXP_S32_PINMUX(0, 0, 93, 5, 0, 0) 1927 #define PTC29_LPI2C1_SDA_I NXP_S32_PINMUX(0, 0, 93, 0, 219, 3) 1928 #define PTD8_LPI2C1_SDA_O NXP_S32_PINMUX(0, 0, 104, 2, 0, 0) 1929 #define PTD8_LPI2C1_SDA_I NXP_S32_PINMUX(0, 0, 104, 0, 219, 1) 1930 #define PTD9_LPI2C1_SCL_O NXP_S32_PINMUX(0, 0, 105, 2, 0, 0) 1931 #define PTD9_LPI2C1_SCL_I NXP_S32_PINMUX(0, 0, 105, 0, 217, 2) 1932 #define PTD12_LPI2C1_HREQ NXP_S32_PINMUX(0, 0, 108, 0, 216, 1) 1933 #define PTF7_LPI2C1_SCL_O NXP_S32_PINMUX(0, 0, 167, 3, 0, 0) 1934 #define PTF7_LPI2C1_SCL_I NXP_S32_PINMUX(0, 0, 167, 0, 217, 5) 1935 #define PTF8_LPI2C1_SDA_O NXP_S32_PINMUX(0, 0, 168, 3, 0, 0) 1936 #define PTF8_LPI2C1_SDA_I NXP_S32_PINMUX(0, 0, 168, 0, 219, 4) 1937 1938 /* CAN2 */ 1939 #define PTC6_CAN2_RX NXP_S32_PINMUX(0, 0, 70, 0, 2, 6) 1940 #define PTC7_CAN2_TX NXP_S32_PINMUX(0, 0, 71, 7, 0, 0) 1941 #define PTC14_CAN2_RX NXP_S32_PINMUX(0, 0, 78, 0, 2, 2) 1942 #define PTC15_CAN2_TX NXP_S32_PINMUX(0, 0, 79, 1, 0, 0) 1943 #define PTC16_CAN2_RX NXP_S32_PINMUX(0, 0, 80, 0, 2, 1) 1944 #define PTC17_CAN2_TX NXP_S32_PINMUX(0, 0, 81, 3, 0, 0) 1945 #define PTD18_CAN2_TX NXP_S32_PINMUX(0, 0, 114, 1, 0, 0) 1946 #define PTD19_CAN2_RX NXP_S32_PINMUX(0, 0, 115, 0, 2, 4) 1947 #define PTE24_CAN2_TX NXP_S32_PINMUX(0, 0, 152, 3, 0, 0) 1948 #define PTE25_CAN2_RX NXP_S32_PINMUX(0, 0, 153, 0, 2, 3) 1949 #define PTF25_CAN2_TX NXP_S32_PINMUX(0, 0, 185, 1, 0, 0) 1950 #define PTF26_CAN2_RX NXP_S32_PINMUX(0, 0, 186, 0, 2, 5) 1951 1952 /* CAN5 */ 1953 #define PTC10_CAN5_TX NXP_S32_PINMUX(0, 0, 74, 3, 0, 0) 1954 #define PTC11_CAN5_RX NXP_S32_PINMUX(0, 0, 75, 0, 5, 2) 1955 #define PTC26_CAN5_RX NXP_S32_PINMUX(0, 0, 90, 0, 5, 5) 1956 #define PTC27_CAN5_TX NXP_S32_PINMUX(0, 0, 91, 1, 0, 0) 1957 #define PTD17_CAN5_RX NXP_S32_PINMUX(0, 0, 113, 0, 5, 1) 1958 #define PTE12_CAN5_TX NXP_S32_PINMUX(0, 0, 140, 2, 0, 0) 1959 #define PTF4_CAN5_TX NXP_S32_PINMUX(0, 0, 164, 1, 0, 0) 1960 #define PTF5_CAN5_RX NXP_S32_PINMUX(0, 0, 165, 0, 5, 3) 1961 #define PTG13_CAN5_TX NXP_S32_PINMUX(0, 0, 205, 1, 0, 0) 1962 #define PTG14_CAN5_RX NXP_S32_PINMUX(0, 0, 206, 0, 5, 4) 1963 1964 /* LPUART10 */ 1965 #define PTC12_LPUART10_RX NXP_S32_PINMUX(0, 0, 76, 0, 197, 2) 1966 #define PTC13_LPUART10_TX_O NXP_S32_PINMUX(0, 0, 77, 1, 0, 0) 1967 #define PTC13_LPUART10_TX_I NXP_S32_PINMUX(0, 0, 77, 0, 373, 1) 1968 #define PTE2_LPUART10_RX NXP_S32_PINMUX(0, 0, 130, 0, 197, 1) 1969 #define PTE6_LPUART10_TX_O NXP_S32_PINMUX(0, 0, 134, 5, 0, 0) 1970 #define PTE6_LPUART10_TX_I NXP_S32_PINMUX(0, 0, 134, 0, 373, 2) 1971 #define PTF12_LPUART10_TX_O NXP_S32_PINMUX(0, 0, 172, 1, 0, 0) 1972 #define PTF12_LPUART10_TX_I NXP_S32_PINMUX(0, 0, 172, 0, 373, 3) 1973 #define PTF13_LPUART10_RX NXP_S32_PINMUX(0, 0, 173, 0, 197, 3) 1974 1975 /* LPUART12 */ 1976 #define PTC24_LPUART12_TX_O NXP_S32_PINMUX(0, 0, 88, 1, 0, 0) 1977 #define PTC24_LPUART12_TX_I NXP_S32_PINMUX(0, 0, 88, 0, 375, 1) 1978 #define PTC25_LPUART12_RX NXP_S32_PINMUX(0, 0, 89, 0, 199, 2) 1979 #define PTE4_LPUART12_TX_O NXP_S32_PINMUX(0, 0, 132, 5, 0, 0) 1980 #define PTE4_LPUART12_TX_I NXP_S32_PINMUX(0, 0, 132, 0, 375, 2) 1981 #define PTE5_LPUART12_RX NXP_S32_PINMUX(0, 0, 133, 0, 199, 1) 1982 #define PTF16_LPUART12_TX_O NXP_S32_PINMUX(0, 0, 176, 1, 0, 0) 1983 #define PTF16_LPUART12_TX_I NXP_S32_PINMUX(0, 0, 176, 0, 375, 3) 1984 #define PTF17_LPUART12_RX NXP_S32_PINMUX(0, 0, 177, 0, 199, 3) 1985 1986 /* SAI1 */ 1987 #define PTD13_SAI1_D0_O NXP_S32_PINMUX(0, 0, 109, 6, 0, 0) 1988 #define PTD13_SAI1_D0_I NXP_S32_PINMUX(0, 0, 109, 0, 323, 1) 1989 #define PTD14_SAI1_MCLK NXP_S32_PINMUX(0, 0, 110, 0, 324, 1) 1990 #define PTD15_SAI1_SYNC_O NXP_S32_PINMUX(0, 0, 111, 6, 0, 0) 1991 #define PTD15_SAI1_SYNC_I NXP_S32_PINMUX(0, 0, 111, 0, 325, 1) 1992 #define PTE8_SAI1_BCLK_O NXP_S32_PINMUX(0, 0, 136, 6, 0, 0) 1993 #define PTE8_SAI1_BCLK_I NXP_S32_PINMUX(0, 0, 136, 0, 322, 1) 1994 1995 /* TRGMUX INTERNAL */ 1996 #define TRGMUX_INT_OUT37_EMIOS_0_CH6_G NXP_S32_PINMUX(0, 0, 17, 0, 54, 3) 1997 #define TRGMUX_INT_OUT38_EMIOS_0_CH7_G NXP_S32_PINMUX(0, 0, 135, 0, 55, 4) 1998 #endif /* HAL_NXP_DTS_NXP_S32_S32K344_257BGA_PINCTRL_H_ */ 1999
