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Searched refs:PORT_GPCLR_GPWE9_MASK (Results 1 – 24 of 24) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h22970 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
22976 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h22970 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
22976 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h22970 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
22976 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h22970 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
22976 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h30207 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
30213 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h30207 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
30213 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h30207 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
30213 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h30825 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
30831 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h30825 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
30831 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h30825 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
30831 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h26105 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
26111 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h28274 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
28280 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h44573 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
44579 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h44543 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
44549 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h33328 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
33334 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
DMCXW727C_cm33_core1.h38523 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
38529 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h55631 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
55637 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
DMCXN546_cm33_core1.h55631 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
55637 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h55631 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
55637 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
DMCXN547_cm33_core1.h55631 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
55637 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h56366 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
56372 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
DMCXN947_cm33_core0.h56366 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
56372 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h56366 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
56372 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)
DMCXN946_cm33_core1.h56366 #define PORT_GPCLR_GPWE9_MASK (0x2000000U) macro
56372 … (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK)