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Searched refs:PMU_REG_3P0_ENABLE_LINREG_MASK (Results 1 – 24 of 24) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/pmu/
Dfsl_pmu.h365 base->REG_3P0 |= PMU_REG_3P0_ENABLE_LINREG_MASK; in PMU_3P0EnableOutput()
369 base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_LINREG_MASK; in PMU_3P0EnableOutput()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/drivers/
Dfsl_clock.c504 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs0Clock()
531 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs1Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/drivers/
Dfsl_clock.c496 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs0Clock()
523 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs1Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/drivers/
Dfsl_clock.c500 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs0Clock()
527 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs1Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/drivers/
Dfsl_clock.c504 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs0Clock()
531 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs1Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/drivers/
Dfsl_clock.c504 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs0Clock()
531 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs1Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/drivers/
Dfsl_clock.c491 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs0Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/drivers/
Dfsl_clock.c491 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs0Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/drivers/
Dfsl_clock.c524 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs0Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/drivers/
Dfsl_clock.c485 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs0Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/drivers/
Dfsl_clock.c498 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs0Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/drivers/
Dfsl_clock.c498 (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); in CLOCK_EnableUsbhs0Clock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h22696 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) macro
22698 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h25306 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) macro
25308 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h29349 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) macro
29351 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h29370 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) macro
29372 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h30421 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) macro
30423 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h31818 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) macro
31820 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h33128 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) macro
33130 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h33669 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) macro
33671 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h32560 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) macro
32562 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h35202 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) macro
35204 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h35195 #define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) macro
35197 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h28663 #define PMU_REG_3P0_ENABLE_LINREG_MASK 0x1u macro