Searched refs:PMU_REG_3P0_ENABLE_ILIMIT_MASK (Results 1 – 13 of 13) sorted by relevance
329 base->REG_3P0 |= PMU_REG_3P0_ENABLE_ILIMIT_MASK; in PMU_3P0EnableCurrentLimit()333 base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_ILIMIT_MASK; in PMU_3P0EnableCurrentLimit()
22704 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro22706 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
25314 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro25316 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
29357 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro29359 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
29378 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro29380 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
30429 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro30431 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
31826 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro31828 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
33136 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro33138 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
33677 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro33679 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
32568 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro32570 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
35210 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro35212 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
35203 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) macro35205 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
28667 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u macro
