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Searched refs:PMU_REG_2P5_OUTPUT_TRG_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/pmu/
Dfsl_pmu.h417 base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_OUTPUT_TRG_MASK) | PMU_REG_2P5_OUTPUT_TRG(value); in PMU_2P5SetRegulatorOutputVoltage()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h22896 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) macro
22903 … (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h25506 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) macro
25513 … (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h29549 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) macro
29556 … (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h29570 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) macro
29577 … (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h30621 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) macro
30628 … (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h32018 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) macro
32025 … (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h33328 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) macro
33335 … (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h33869 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) macro
33876 … (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h32760 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) macro
32767 … (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h35402 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) macro
35409 … (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h35395 #define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) macro
35402 … (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h28693 #define PMU_REG_2P5_OUTPUT_TRG_MASK 0x1F00u macro
28695 … (((uint32_t)(((uint32_t)(x))<<PMU_REG_2P5_OUTPUT_TRG_SHIFT))&PMU_REG_2P5_OUTPUT_TRG_MASK)