Searched refs:PMU_REG_1P1_ENABLE_ILIMIT_MASK (Results 1 – 13 of 13) sorted by relevance
220 base->REG_1P1 |= PMU_REG_1P1_ENABLE_ILIMIT_MASK; in PMU_1P1EnableCurrentLimit()224 base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_ILIMIT_MASK; in PMU_1P1EnableCurrentLimit()
22492 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) macro22494 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
25102 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) macro25104 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
29145 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) macro29147 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
29166 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) macro29168 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
30217 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) macro30219 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
31614 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) macro31616 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
32924 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) macro32926 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
33465 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) macro33467 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
32356 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) macro32358 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
34998 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) macro35000 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
34991 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) macro34993 …(((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
28644 #define PMU_REG_1P1_ENABLE_ILIMIT_MASK 0x4u macro
