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Searched refs:PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h24515 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) macro
24521 …t32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h27125 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) macro
27131 …t32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h31168 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) macro
31174 …t32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h31189 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) macro
31195 …t32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h32562 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) macro
32568 …t32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h33951 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) macro
33957 …t32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h35269 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) macro
35275 …t32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h35802 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) macro
35808 …t32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h34701 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) macro
34707 …t32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h37343 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) macro
37349 …t32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h37336 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) macro
37342 …t32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h29002 #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK 0x700u macro
29004 …(uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT))&PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)