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Searched refs:PMU_MISC2_SET_REG0_BO_OFFSET_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h24268 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) macro
24274 …t32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h26878 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) macro
26884 …t32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h30921 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) macro
30927 …t32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h30942 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) macro
30948 …t32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h32295 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) macro
32301 …t32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h33684 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) macro
33690 …t32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h35002 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) macro
35008 …t32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h35535 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) macro
35541 …t32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h34434 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) macro
34440 …t32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h37076 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) macro
37082 …t32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h37069 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) macro
37075 …t32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h28909 #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK 0x7u macro
28911 …(uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT))&PMU_MISC2_SET_REG0_BO_OFFSET_MASK)