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Searched refs:PMU_MISC2_REG2_BO_OFFSET_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h24206 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) macro
24212 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h26816 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) macro
26822 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h30859 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) macro
30865 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h30880 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) macro
30886 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h32223 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) macro
32229 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h33612 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) macro
33618 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h34930 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) macro
34936 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h35463 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) macro
35469 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h34362 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) macro
34368 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h37004 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) macro
37010 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h36997 #define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) macro
37003 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h28885 #define PMU_MISC2_REG2_BO_OFFSET_MASK 0x70000u macro
28887 … (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_REG2_BO_OFFSET_SHIFT))&PMU_MISC2_REG2_BO_OFFSET_MASK)