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Searched refs:PMU_MISC2_CLR_VIDEO_DIV_MASK (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h32525 #define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) macro
32533 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h33914 #define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) macro
33922 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h35232 #define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) macro
35240 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h35765 #define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) macro
35773 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h34664 #define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) macro
34672 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h37306 #define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) macro
37314 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h37299 #define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) macro
37307 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h28989 #define PMU_MISC2_CLR_VIDEO_DIV_MASK 0xC0000000u macro
28991 … (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_VIDEO_DIV_SHIFT))&PMU_MISC2_CLR_VIDEO_DIV_MASK)