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Searched refs:PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h31904 #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) macro
31929 …int32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h33298 #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) macro
33322 …int32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h34611 #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) macro
34636 …int32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h35149 #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) macro
35173 …int32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h34043 #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) macro
34068 …int32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h36685 #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) macro
36710 …int32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h36678 #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) macro
36703 …int32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h28783 #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK 0x3E0u macro
28785 …(((uint32_t)(((uint32_t)(x))<<PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT))&PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)