Searched refs:PMU_MISC1_SET_IRQ_TEMPLOW_MASK (Results 1 – 12 of 12) sorted by relevance
24072 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) macro24074 …(((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
26682 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) macro26684 …(((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
30725 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) macro30727 …(((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
30746 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) macro30748 …(((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
31959 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) macro31961 …(((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
33352 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) macro33354 …(((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
34666 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) macro34668 …(((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
35203 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) macro35205 …(((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
34098 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) macro34100 …(((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
36740 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) macro36742 …(((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
36733 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) macro36735 …(((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
28800 #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK 0x10000000u macro
