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Searched refs:PMU_MISC1_LVDSCLK2_IBEN_MASK (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h31846 #define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) macro
31848 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h33241 #define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) macro
33243 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h34553 #define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) macro
34555 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h35092 #define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) macro
35094 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h33985 #define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) macro
33987 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h36627 #define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) macro
36629 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h36620 #define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) macro
36622 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h28763 #define PMU_MISC1_LVDSCLK2_IBEN_MASK 0x2000u macro