Searched refs:PMU_MISC1_LVDS2_CLK_SEL_MASK (Results 1 – 8 of 8) sorted by relevance
31807 #define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) macro31832 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
33203 #define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) macro33227 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
34514 #define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) macro34539 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
35054 #define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) macro35078 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
33946 #define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) macro33971 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
36588 #define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) macro36613 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
36581 #define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) macro36606 … (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
28754 #define PMU_MISC1_LVDS2_CLK_SEL_MASK 0x3E0u macro28756 … (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_LVDS2_CLK_SEL_SHIFT))&PMU_MISC1_LVDS2_CLK_SEL_MASK)
