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Searched refs:PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h31979 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) macro
31999 …int32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h33372 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) macro
33391 …int32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h34686 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) macro
34706 …int32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h35223 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) macro
35242 …int32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h34118 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) macro
34138 …int32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h36760 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) macro
36780 …int32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h36753 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) macro
36773 …int32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h28809 #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK 0x1Fu macro
28811 …(((uint32_t)(((uint32_t)(x))<<PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT))&PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)