Home
last modified time | relevance | path

Searched refs:PMU_LDO_PLL (Results 1 – 25 of 36) sorted by relevance

12

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_pmu.c68 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
72 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
274 ANADIG_PMU->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_STBY_EN_MASK; in PMU_EnableLdoStandbyMode()
278 ANADIG_PMU->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_STBY_EN_MASK; in PMU_EnableLdoStandbyMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_pmu.c68 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
72 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
274 ANADIG_PMU->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_STBY_EN_MASK; in PMU_EnableLdoStandbyMode()
278 ANADIG_PMU->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_STBY_EN_MASK; in PMU_EnableLdoStandbyMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_pmu.c68 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
72 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
274 ANADIG_PMU->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_STBY_EN_MASK; in PMU_EnableLdoStandbyMode()
278 ANADIG_PMU->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_STBY_EN_MASK; in PMU_EnableLdoStandbyMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_pmu.c68 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
72 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
274 ANADIG_PMU->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_STBY_EN_MASK; in PMU_EnableLdoStandbyMode()
278 ANADIG_PMU->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_STBY_EN_MASK; in PMU_EnableLdoStandbyMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_pmu.c163 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
167 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
180 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
184 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
Dfsl_anatop_ai.c33 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
47 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_pmu.c163 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
167 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
180 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
184 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
Dfsl_anatop_ai.c33 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
47 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_pmu.c163 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
167 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
180 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
184 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
Dfsl_anatop_ai.c33 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
47 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_pmu.c163 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
167 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
180 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
184 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
Dfsl_anatop_ai.c33 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
47 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_pmu.c163 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
167 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
180 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
184 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
Dfsl_anatop_ai.c33 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
47 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_pmu.c163 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
167 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
180 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
184 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
Dfsl_anatop_ai.c33 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
47 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_pmu.c163 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
167 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; in PMU_SetPllLdoControlMode()
180 base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
184 base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; in PMU_SwitchPllLdoToGPCMode()
Dfsl_anatop_ai.c33 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
47 … ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ in ANATOP_AI_Access()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm4.h6044 __IO uint32_t PMU_LDO_PLL; /**< PMU_LDO_PLL_REGISTER, offset: 0x500 */ member
DMIMXRT1165_cm7.h6047 __IO uint32_t PMU_LDO_PLL; /**< PMU_LDO_PLL_REGISTER, offset: 0x500 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h6056 __IO uint32_t PMU_LDO_PLL; /**< PMU_LDO_PLL_REGISTER, offset: 0x500 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h6053 __IO uint32_t PMU_LDO_PLL; /**< PMU_LDO_PLL_REGISTER, offset: 0x500 */ member
DMIMXRT1175_cm7.h6056 __IO uint32_t PMU_LDO_PLL; /**< PMU_LDO_PLL_REGISTER, offset: 0x500 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm7.h6068 __IO uint32_t PMU_LDO_PLL; /**< PMU_LDO_PLL_REGISTER, offset: 0x500 */ member
DMIMXRT1173_cm4.h6065 __IO uint32_t PMU_LDO_PLL; /**< PMU_LDO_PLL_REGISTER, offset: 0x500 */ member

12