Home
last modified time | relevance | path

Searched refs:PMC_PDSLEEPCFG4_GPU_MASK (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT735S/
Dfsl_pm_device.c237 [kResc_SRAM_GPU - RESC_GROUP_SRAMS_START] = {5U, PMC_PDSLEEPCFG4_GPU_MASK},
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT758S/
Dfsl_pm_device.c237 [kResc_SRAM_GPU - RESC_GROUP_SRAMS_START] = {5U, PMC_PDSLEEPCFG4_GPU_MASK},
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT798S/
Dfsl_pm_device.c237 [kResc_SRAM_GPU - RESC_GROUP_SRAMS_START] = {5U, PMC_PDSLEEPCFG4_GPU_MASK},
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h38709 #define PMC_PDSLEEPCFG4_GPU_MASK (0x80U) macro
38715 … (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)
DMIMXRT735S_cm33_core1.h38769 #define PMC_PDSLEEPCFG4_GPU_MASK (0x80U) macro
38775 … (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)
DMIMXRT735S_ezhv.h54476 #define PMC_PDSLEEPCFG4_GPU_MASK (0x80U) macro
54482 … (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)
DMIMXRT735S_cm33_core0.h54523 #define PMC_PDSLEEPCFG4_GPU_MASK (0x80U) macro
54529 … (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h41566 #define PMC_PDSLEEPCFG4_GPU_MASK (0x80U) macro
41572 … (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)
DMIMXRT758S_hifi1.h41504 #define PMC_PDSLEEPCFG4_GPU_MASK (0x80U) macro
41510 … (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)
DMIMXRT758S_cm33_core0.h57322 #define PMC_PDSLEEPCFG4_GPU_MASK (0x80U) macro
57328 … (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)
DMIMXRT758S_ezhv.h57214 #define PMC_PDSLEEPCFG4_GPU_MASK (0x80U) macro
57220 … (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h41504 #define PMC_PDSLEEPCFG4_GPU_MASK (0x80U) macro
41510 … (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)
DMIMXRT798S_cm33_core1.h41566 #define PMC_PDSLEEPCFG4_GPU_MASK (0x80U) macro
41572 … (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)
DMIMXRT798S_hifi4.h57237 #define PMC_PDSLEEPCFG4_GPU_MASK (0x80U) macro
57243 … (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)
DMIMXRT798S_cm33_core0.h57322 #define PMC_PDSLEEPCFG4_GPU_MASK (0x80U) macro
57328 … (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)
DMIMXRT798S_ezhv.h57238 #define PMC_PDSLEEPCFG4_GPU_MASK (0x80U) macro
57244 … (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG4_GPU_SHIFT)) & PMC_PDSLEEPCFG4_GPU_MASK)