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Searched refs:PMC_PDCFGSTATUS5_NPU_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h40201 #define PMC_PDCFGSTATUS5_NPU_MASK (0x20000U) macro
40207 … (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)
DMIMXRT735S_cm33_core1.h40261 #define PMC_PDCFGSTATUS5_NPU_MASK (0x20000U) macro
40267 … (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)
DMIMXRT735S_ezhv.h55968 #define PMC_PDCFGSTATUS5_NPU_MASK (0x20000U) macro
55974 … (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)
DMIMXRT735S_cm33_core0.h56015 #define PMC_PDCFGSTATUS5_NPU_MASK (0x20000U) macro
56021 … (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h43058 #define PMC_PDCFGSTATUS5_NPU_MASK (0x20000U) macro
43064 … (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)
DMIMXRT758S_hifi1.h42996 #define PMC_PDCFGSTATUS5_NPU_MASK (0x20000U) macro
43002 … (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)
DMIMXRT758S_cm33_core0.h58814 #define PMC_PDCFGSTATUS5_NPU_MASK (0x20000U) macro
58820 … (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)
DMIMXRT758S_ezhv.h58706 #define PMC_PDCFGSTATUS5_NPU_MASK (0x20000U) macro
58712 … (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h42996 #define PMC_PDCFGSTATUS5_NPU_MASK (0x20000U) macro
43002 … (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)
DMIMXRT798S_cm33_core1.h43058 #define PMC_PDCFGSTATUS5_NPU_MASK (0x20000U) macro
43064 … (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)
DMIMXRT798S_hifi4.h58729 #define PMC_PDCFGSTATUS5_NPU_MASK (0x20000U) macro
58735 … (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)
DMIMXRT798S_cm33_core0.h58814 #define PMC_PDCFGSTATUS5_NPU_MASK (0x20000U) macro
58820 … (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)
DMIMXRT798S_ezhv.h58730 #define PMC_PDCFGSTATUS5_NPU_MASK (0x20000U) macro
58736 … (((uint32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS5_NPU_SHIFT)) & PMC_PDCFGSTATUS5_NPU_MASK)