Searched refs:PMC_PDCFGSTATUS0_V2NMED_DSR_MASK (Results 1 – 13 of 13) sorted by relevance
39071 #define PMC_PDCFGSTATUS0_V2NMED_DSR_MASK (0x40U) macro39077 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2NMED_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2NMED_DSR_MASK)
39131 #define PMC_PDCFGSTATUS0_V2NMED_DSR_MASK (0x40U) macro39137 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2NMED_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2NMED_DSR_MASK)
54838 #define PMC_PDCFGSTATUS0_V2NMED_DSR_MASK (0x40U) macro54844 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2NMED_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2NMED_DSR_MASK)
54885 #define PMC_PDCFGSTATUS0_V2NMED_DSR_MASK (0x40U) macro54891 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2NMED_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2NMED_DSR_MASK)
41928 #define PMC_PDCFGSTATUS0_V2NMED_DSR_MASK (0x40U) macro41934 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2NMED_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2NMED_DSR_MASK)
41866 #define PMC_PDCFGSTATUS0_V2NMED_DSR_MASK (0x40U) macro41872 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2NMED_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2NMED_DSR_MASK)
57684 #define PMC_PDCFGSTATUS0_V2NMED_DSR_MASK (0x40U) macro57690 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2NMED_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2NMED_DSR_MASK)
57576 #define PMC_PDCFGSTATUS0_V2NMED_DSR_MASK (0x40U) macro57582 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2NMED_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2NMED_DSR_MASK)
57599 #define PMC_PDCFGSTATUS0_V2NMED_DSR_MASK (0x40U) macro57605 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2NMED_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2NMED_DSR_MASK)
57600 #define PMC_PDCFGSTATUS0_V2NMED_DSR_MASK (0x40U) macro57606 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2NMED_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2NMED_DSR_MASK)
