Searched refs:PMC_PDCFGSTATUS0_V2COMP_DSR_MASK (Results 1 – 13 of 13) sorted by relevance
39063 #define PMC_PDCFGSTATUS0_V2COMP_DSR_MASK (0x20U) macro39069 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2COMP_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2COMP_DSR_MASK)
39123 #define PMC_PDCFGSTATUS0_V2COMP_DSR_MASK (0x20U) macro39129 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2COMP_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2COMP_DSR_MASK)
54830 #define PMC_PDCFGSTATUS0_V2COMP_DSR_MASK (0x20U) macro54836 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2COMP_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2COMP_DSR_MASK)
54877 #define PMC_PDCFGSTATUS0_V2COMP_DSR_MASK (0x20U) macro54883 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2COMP_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2COMP_DSR_MASK)
41920 #define PMC_PDCFGSTATUS0_V2COMP_DSR_MASK (0x20U) macro41926 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2COMP_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2COMP_DSR_MASK)
41858 #define PMC_PDCFGSTATUS0_V2COMP_DSR_MASK (0x20U) macro41864 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2COMP_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2COMP_DSR_MASK)
57676 #define PMC_PDCFGSTATUS0_V2COMP_DSR_MASK (0x20U) macro57682 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2COMP_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2COMP_DSR_MASK)
57568 #define PMC_PDCFGSTATUS0_V2COMP_DSR_MASK (0x20U) macro57574 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2COMP_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2COMP_DSR_MASK)
57591 #define PMC_PDCFGSTATUS0_V2COMP_DSR_MASK (0x20U) macro57597 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2COMP_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2COMP_DSR_MASK)
57592 #define PMC_PDCFGSTATUS0_V2COMP_DSR_MASK (0x20U) macro57598 …int32_t)(((uint32_t)(x)) << PMC_PDCFGSTATUS0_V2COMP_DSR_SHIFT)) & PMC_PDCFGSTATUS0_V2COMP_DSR_MASK)
