PLL_CTRL (reference) in projects: hal_nxp-latest

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Searched refs:PLL_CTRL (Results 1 – 25 of 56) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/drivers/
D	fsl_clock.h	737 …kCLOCK_ArmPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL G… 739 …kCLOCK_GpuPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL … 740 …kCLOCK_VpuPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL … 741 …kCLOCK_DramPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PLL… 743 …kCLOCK_SysPll1Gate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM P… 745 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 747 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 749 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 751 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 753 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/drivers/
D	fsl_clock.h	845 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 847 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 848 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 849 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 851 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 853 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 855 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 857 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 859 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 861 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM4/drivers/
D	fsl_clock.h	840 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 842 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 843 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 844 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 846 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 848 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 850 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 852 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 854 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 856 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/drivers/
D	fsl_clock.h	845 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 847 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 848 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 849 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 851 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 853 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 855 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 857 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 859 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 861 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/drivers/
D	fsl_clock.h	737 …kCLOCK_ArmPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL G… 739 …kCLOCK_GpuPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL … 740 …kCLOCK_VpuPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL … 741 …kCLOCK_DramPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PLL… 743 …kCLOCK_SysPll1Gate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM P… 745 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 747 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 749 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 751 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 753 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/drivers/
D	fsl_clock.h	845 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 847 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 848 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 849 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 851 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 853 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 855 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 857 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 859 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 861 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/drivers/
D	fsl_clock.h	840 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 842 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 843 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 844 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 846 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 848 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 850 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 852 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 854 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 856 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/drivers/
D	fsl_clock.h	845 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 847 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 848 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 849 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 851 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 853 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 855 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 857 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 859 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 861 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/drivers/
D	fsl_clock.h	737 …kCLOCK_ArmPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL G… 739 …kCLOCK_GpuPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL … 740 …kCLOCK_VpuPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL … 741 …kCLOCK_DramPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PLL… 743 …kCLOCK_SysPll1Gate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM P… 745 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 747 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 749 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 751 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 753 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/drivers/
D	fsl_clock.h	840 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 842 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 843 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 844 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 846 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 848 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 850 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 852 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 854 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 856 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/drivers/
D	fsl_clock.h	840 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 842 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 843 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 844 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 846 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 848 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 850 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 852 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 854 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 856 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/drivers/
D	fsl_clock.h	845 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 847 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 848 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 849 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 851 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 853 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 855 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 857 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 859 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 861 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM2/drivers/
D	fsl_clock.h	840 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 842 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 843 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 844 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 846 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 848 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 850 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 852 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 854 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 856 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/drivers/
D	fsl_clock.h	840 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 842 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 843 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 844 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 846 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 848 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 850 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 852 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 854 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 856 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/drivers/
D	fsl_clock.h	737 …kCLOCK_ArmPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL G… 739 …kCLOCK_GpuPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL … 740 …kCLOCK_VpuPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL … 741 …kCLOCK_DramPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PLL… 743 …kCLOCK_SysPll1Gate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM P… 745 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 747 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 749 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 751 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 753 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/drivers/
D	fsl_clock.h	845 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 847 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 848 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 849 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 851 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 853 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 855 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 857 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 859 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 861 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/drivers/
D	fsl_clock.h	737 …kCLOCK_ArmPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL G… 739 …kCLOCK_GpuPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL … 740 …kCLOCK_VpuPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL … 741 …kCLOCK_DramPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PLL… 743 …kCLOCK_SysPll1Gate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM P… 745 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 747 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 749 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 751 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 753 … (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/drivers/
D	fsl_clock.h	1101 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 1103 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 1104 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 1105 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 1107 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 1109 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 1111 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 1113 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 1115 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 1117 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/drivers/
D	fsl_clock.h	1101 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 1103 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 1104 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 1105 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 1107 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 1109 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 1111 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 1113 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 1115 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 1117 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/drivers/
D	fsl_clock.h	1101 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 1103 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 1104 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 1105 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 1107 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 1109 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 1111 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 1113 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 1115 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 1117 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/drivers/
D	fsl_clock.h	1109 …kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /!< ARM PLL … 1111 …kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /!< GPU PLL… 1112 …kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /!< VPU PLL… 1113 …kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /!< DRAM PL… 1115 …kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /!< SYSTEM … 1117 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /!< SYSTEM PLL1 Div2 Gate./ 1119 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /!< SYSTEM PLL1 Div3 Gate./ 1121 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /!< SYSTEM PLL1 Div4 Gate./ 1123 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /!< SYSTEM PLL1 Div5 Gate./ 1125 … (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /!< SYSTEM PLL1 Div6 Gate.*/ [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/
D	fsl_clock.c	180 …steps = (SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_FBDIV_MASK) >> SYSCTL2_PLL_CTRL_TCPU_FBDIV_SHIF… in CLOCK_GetTcpuFvcoFreq() 217 …(SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_MASK) >> SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_… in CLOCK_GetTcpuMciFlexspiClkFreq() 228 …(SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL_MASK) >> SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_… in CLOCK_GetTddrMciFlexspiClkFreq() 1208 SYSCTL2->PLL_CTRL = in CLOCK_CfgTcpuRefClk() 1209 …(SYSCTL2->PLL_CTRL & ~(SYSCTL2_PLL_CTRL_TCPU_FBDIV_MASK \| SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_MA… in CLOCK_CfgTcpuRefClk() 1226 if ((SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_PDB_MASK) != 0U) in CLOCK_InitTcpuRefClk() 1235 SYSCTL2->PLL_CTRL \|= SYSCTL2_PLL_CTRL_TCPU_PDB_MASK; in CLOCK_InitTcpuRefClk() 1237 while ((SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_LOCK_MASK) == 0U) in CLOCK_InitTcpuRefClk() 1253 SYSCTL2->PLL_CTRL &= ~SYSCTL2_PLL_CTRL_TCPU_PDB_MASK; in CLOCK_DeinitTcpuRefClk() 1267 if ((SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TDDR_PDB_MASK) != 0U) in CLOCK_InitTddrRefClk() [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/
D	fsl_clock.c	180 …steps = (SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_FBDIV_MASK) >> SYSCTL2_PLL_CTRL_TCPU_FBDIV_SHIF… in CLOCK_GetTcpuFvcoFreq() 217 …(SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_MASK) >> SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_… in CLOCK_GetTcpuMciFlexspiClkFreq() 228 …(SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_CLK_SEL_MASK) >> SYSCTL2_PLL_CTRL_TDDR_FLEXSPI_… in CLOCK_GetTddrMciFlexspiClkFreq() 1208 SYSCTL2->PLL_CTRL = in CLOCK_CfgTcpuRefClk() 1209 …(SYSCTL2->PLL_CTRL & ~(SYSCTL2_PLL_CTRL_TCPU_FBDIV_MASK \| SYSCTL2_PLL_CTRL_TCPU_FLEXSPI_CLK_SEL_MA… in CLOCK_CfgTcpuRefClk() 1226 if ((SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_PDB_MASK) != 0U) in CLOCK_InitTcpuRefClk() 1235 SYSCTL2->PLL_CTRL \|= SYSCTL2_PLL_CTRL_TCPU_PDB_MASK; in CLOCK_InitTcpuRefClk() 1237 while ((SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_LOCK_MASK) == 0U) in CLOCK_InitTcpuRefClk() 1253 SYSCTL2->PLL_CTRL &= ~SYSCTL2_PLL_CTRL_TCPU_PDB_MASK; in CLOCK_DeinitTcpuRefClk() 1267 if ((SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TDDR_PDB_MASK) != 0U) in CLOCK_InitTddrRefClk() [all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
D	system_RW610.c	`137 …steps = (SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_FBDIV_MASK) >> SYSCTL2_PLL_CTRL_TCPU_FBDIV_SHIF… in getTcpuFvcoFreq()`
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
D	system_RW612.c	`137 …steps = (SYSCTL2->PLL_CTRL & SYSCTL2_PLL_CTRL_TCPU_FBDIV_MASK) >> SYSCTL2_PLL_CTRL_TCPU_FBDIV_SHIF… in getTcpuFvcoFreq()`

12 3

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