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Searched refs:PHY_SS_CTRL (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/ldb/
Dfsl_ldb.c135 base->PHY_SS_CTRL = 0U; in LDB_Init()
146 base->PHY_SS_CTRL = 0U; in LDB_Init()
217 …reg = base->PHY_SS_CTRL & ~(LDB_SS_CTRL_CH_VSYNC_POL_MASK(channel) | LDB_SS_CTRL_CH_HSYNC_POL_MASK… in LDB_InitChannel()
229 base->PHY_SS_CTRL = reg; in LDB_InitChannel()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_dsp.h64030 …__IO uint32_t PHY_SS_CTRL; /**< Channel n Interrupt Pending Register, offset… member
DMIMX8QM6_cm4_core1.h75013 __IO uint32_t PHY_SS_CTRL; member
DMIMX8QM6_cm4_core0.h75013 __IO uint32_t PHY_SS_CTRL; member