Searched refs:PHY_BCTL_RESET_MASK (Results 1 – 15 of 15) sorted by relevance
| /hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyar8031/ |
| D | fsl_phyar8031.c | 144 result = PHY_AR8031_WRITE(handle, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); in PHY_AR8031_Init()
447 … regValue = PHY_BCTL_SPEED1_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_RESET_MASK; in PHY_AR8031_EnableLoopback()
451 … regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_RESET_MASK; in PHY_AR8031_EnableLoopback()
455 regValue = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_RESET_MASK; in PHY_AR8031_EnableLoopback()
495 regValue = PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESET_MASK; in PHY_AR8031_EnableLoopback()
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| /hal_nxp-latest/mcux/mcux-sdk/components/phylan8720a/ |
| D | fsl_phy.c | 62 (void)PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); in PHY_Init()
66 } while ((delay-- != 0U) && ((reg & PHY_BCTL_RESET_MASK) != 0U)); in PHY_Init()
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| D | fsl_phy.h | 41 #define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ macro
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| /hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phylan8720a/ |
| D | fsl_phylan8720a.c | 92 result = PHY_LAN8720A_WRITE(handle, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); in PHY_LAN8720A_Init()
104 } while ((counter-- != 0U) && (regValue & PHY_BCTL_RESET_MASK) != 0U); in PHY_LAN8720A_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phylan8741/ |
| D | fsl_phylan8741.c | 106 result = PHY_LAN8741_WRITE(handle, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); in PHY_LAN8741_Init()
118 } while ((counter-- != 0U) && (regValue & PHY_BCTL_RESET_MASK) != 0U); in PHY_LAN8741_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyrtl8201/ |
| D | fsl_phyrtl8201.c | 105 result = PHY_RTL8201_WRITE(handle, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); in PHY_RTL8201_Init()
118 } while ((regValue & PHY_BCTL_RESET_MASK) != 0U); in PHY_RTL8201_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyrtl8211f/ |
| D | fsl_phyrtl8211f.c | 126 result = PHY_RTL8211F_WRITE(handle, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); in PHY_RTL8211F_Init()
139 } while ((regValue & PHY_BCTL_RESET_MASK) != 0U); in PHY_RTL8211F_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/components/phyksz8081/ |
| D | fsl_phy.h | 42 #define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ macro
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| D | fsl_phy.c | 60 result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); in PHY_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/cmsis_drivers/enet/ |
| D | fsl_enet_phy_cmsis.c | 49 result = PHY_Write(&phyHandle, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); in PHY_SetForcedSpeedDuplexMode()
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| /hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phydp83848/ |
| D | fsl_phydp83848.c | 77 …esult = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); in PHY_DP83848_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyksz8041/ |
| D | fsl_phyksz8041.c | 85 result = PHY_KSZ8041_WRITE(handle, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); in PHY_KSZ8041_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/components/phy/ |
| D | fsl_phy.h | 43 #define PHY_BCTL_RESET_MASK ((uint16_t)0x8000U) /*!< The PHY reset bit mask. */ macro
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| /hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyksz8081/ |
| D | fsl_phyksz8081.c | 96 result = PHY_KSZ8081_WRITE(handle, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); in PHY_KSZ8081_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/components/phy/device/phyvsc8541/ |
| D | fsl_phyvsc8541.c | 110 result = PHY_VSC8541_WRITE(handle, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); in PHY_VSC8541_Init()
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