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Searched refs:PGC_CPU_PUPSCR_SW2ISO_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h22216 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) macro
22218 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h24826 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) macro
24828 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h28869 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) macro
28871 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h28890 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) macro
28892 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h29941 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) macro
29943 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h31338 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) macro
31340 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h32648 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) macro
32650 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h33189 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) macro
33191 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h32080 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) macro
32082 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h34722 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) macro
34724 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h34715 #define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) macro
34717 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h28468 #define PGC_CPU_PUPSCR_SW2ISO_MASK 0x3F00u macro
28470 … (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PUPSCR_SW2ISO_SHIFT))&PGC_CPU_PUPSCR_SW2ISO_MASK)