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Searched refs:PGC_CPU_PDNSCR_ISO2SW_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h22228 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) macro
22230 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h24838 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) macro
24840 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h28881 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) macro
28883 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h28902 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) macro
28904 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h29953 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) macro
29955 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h31350 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) macro
31352 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h32660 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) macro
32662 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h33201 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) macro
33203 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h32092 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) macro
32094 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h34734 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) macro
34736 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h34727 #define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) macro
34729 … (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h28475 #define PGC_CPU_PDNSCR_ISO2SW_MASK 0x3F00u macro
28477 … (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PDNSCR_ISO2SW_SHIFT))&PGC_CPU_PDNSCR_ISO2SW_MASK)