| /hal_nxp-latest/mcux/mcux-sdk/drivers/wuu/ |
| D | fsl_wuu.c | 80 edgeRegBase = &base->PE1; in WUU_SetExternalWakeUpPinsConfig()
112 edgeRegBase = &base->PE1; in WUU_SetExternalWakeUpPinsConfig()
131 base->PE1 &= ~(WUU_PE_REG_BIT_FIELD_MASK << (2UL * (uint32_t)pinIndex)); in WUU_ClearExternalWakeupPinsConfig()
136 base->PE1 &= ~(WUU_PE_REG_BIT_FIELD_MASK << (2UL * (uint32_t)((uint32_t)pinIndex % 16UL))); in WUU_ClearExternalWakeupPinsConfig()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/llwu/ |
| D | fsl_llwu.c | 37 regBase = &base->PE1; in LLWU_SetExternalWakeupPinMode()
64 regBase = &base->PE1; in LLWU_SetExternalWakeupPinMode()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC041/ |
| D | MCXC041.h | 1874 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKL17Z644/ |
| D | MKL17Z644.h | 3130 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC141/ |
| D | MCXC141.h | 3484 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC142/ |
| D | MCXC142.h | 3482 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/ |
| D | MKL25Z4.h | 1665 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC242/ |
| D | MCXC242.h | 3484 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKL27Z644/ |
| D | MKL27Z644.h | 3139 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC144/ |
| D | MCXC144.h | 4075 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC143/ |
| D | MCXC143.h | 4075 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/ |
| D | MK02F12810.h | 5551 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC243/ |
| D | MCXC243.h | 4073 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXC244/ |
| D | MCXC244.h | 4075 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKV30F12810/ |
| D | MKV30F12810.h | 5556 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z7/ |
| D | MKV10Z7.h | 4982 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F12810/ |
| D | MKV31F12810.h | 5587 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z1287/ |
| D | MKV10Z1287.h | 5470 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/ |
| D | MKW30Z4.h | 3010 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
3033 #define LLWU_PE1_REG(base) ((base)->PE1)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/ |
| D | MKW20Z4.h | 3010 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
3033 #define LLWU_PE1_REG(base) ((base)->PE1)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/ |
| D | MKW40Z4.h | 3010 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
3033 #define LLWU_PE1_REG(base) ((base)->PE1)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKM14ZA5/ |
| D | MKM14ZA5.h | 5163 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKV11Z7/ |
| D | MKV11Z7.h | 6258 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F25612/ |
| D | MKV31F25612.h | 6350 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F51212/ |
| D | MKV31F51212.h | 6596 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ member
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