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Searched refs:PDRUNCFG0_CLR (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_power.c971 SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD_MASK; in AT_QUICKACCESS_SECTION_CODE()
984 SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_MASK; in AT_QUICKACCESS_SECTION_CODE()
1057 SYSCTL0->PDRUNCFG0_CLR = pll_need_pd; in AT_QUICKACCESS_SECTION_CODE()
Dfsl_clock.c1412 …SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_InitSysPll()
1503 …SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
Dfsl_power.h29 #define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + (…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_power.c971 SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD_MASK; in AT_QUICKACCESS_SECTION_CODE()
984 SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_MASK; in AT_QUICKACCESS_SECTION_CODE()
1057 SYSCTL0->PDRUNCFG0_CLR = pll_need_pd; in AT_QUICKACCESS_SECTION_CODE()
Dfsl_clock.c1412 …SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_InitSysPll()
1503 …SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
Dfsl_power.h29 #define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + (…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_power.c971 SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_CLR_LPOSC_PD_MASK; in AT_QUICKACCESS_SECTION_CODE()
984 SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_MASK; in AT_QUICKACCESS_SECTION_CODE()
1057 SYSCTL0->PDRUNCFG0_CLR = pll_need_pd; in AT_QUICKACCESS_SECTION_CODE()
Dfsl_clock.c1412 …SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_InitSysPll()
1503 …SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
Dfsl_power.h29 #define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + (…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_power.c901 SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_MASK; in POWER_EnterDeepSleep()
963 SYSCTL0->PDRUNCFG0_CLR = pll_need_pd; in POWER_EnterDeepSleep()
Dfsl_clock.c1292 …SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_InitSysPll()
1381 …SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
Dfsl_power.h28 #define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + (…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_power.c901 SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_CLR_FFRO_PD_MASK; in POWER_EnterDeepSleep()
963 SYSCTL0->PDRUNCFG0_CLR = pll_need_pd; in POWER_EnterDeepSleep()
Dfsl_clock.c1292 …SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK; in CLOCK_InitSysPll()
1381 …SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK; in CLOCK_InitAudioPll()
Dfsl_power.h28 #define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + (…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h21091 __O uint32_t PDRUNCFG0_CLR; /**< Run configuration 0 clear, offset: 0x630 */ member
DMIMXRT685S_cm33.h30704 __O uint32_t PDRUNCFG0_CLR; /**< Run configuration 0 clear, offset: 0x630 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h30704 __O uint32_t PDRUNCFG0_CLR; /**< Run configuration 0 clear, offset: 0x630 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h34034 __O uint32_t PDRUNCFG0_CLR; /**< Run configuration 0 clear, offset: 0x630 */ member
DMIMXRT595S_cm33.h43833 __O uint32_t PDRUNCFG0_CLR; /**< Run configuration 0 clear, offset: 0x630 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h42206 __O uint32_t PDRUNCFG0_CLR; /**< Run configuration 0 clear, offset: 0x630 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h43832 __O uint32_t PDRUNCFG0_CLR; /**< Run configuration 0 clear, offset: 0x630 */ member