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Searched refs:PDM_VAD0_ZCD_VADZCDAND_MASK (Results 1 – 25 of 68) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/pdm/
Dfsl_pdm.c870 … PDM_VAD0_ZCD_VADZCDAUTO_MASK | PDM_VAD0_ZCD_VADZCDAND_MASK))); in PDM_SetHwvadZeroCrossDetectorConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h43327 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
43333 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h43325 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
43331 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h43325 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
43331 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h34845 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
34851 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
DMIMXRT735S_cm33_core1.h34905 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
34911 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
DMIMXRT735S_ezhv.h50088 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
50094 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
DMIMXRT735S_cm33_core0.h50112 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
50118 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h43327 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
43333 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h43327 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
43333 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h43325 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
43331 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
DMIMX8MN6_ca53.h43339 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
43345 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h37702 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
37708 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
DMIMXRT758S_hifi1.h37640 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
37646 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
DMIMXRT758S_cm33_core0.h52911 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
52917 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h37640 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
37646 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
DMIMXRT798S_cm33_core1.h37702 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
37708 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
DMIMXRT798S_hifi4.h52826 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
52832 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
DMIMXRT798S_cm33_core0.h52911 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
52917 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h60074 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
60080 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
DMIMXRT1175_cm7.h59172 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
59178 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h58648 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
58654 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
DMIMXRT1165_cm4.h59550 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
59556 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h59172 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
59178 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h61822 #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) macro
61828 … (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)

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