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Searched refs:PDM_VAD0_SCONFIG_VADSFILEN_MASK (Results 1 – 25 of 69) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/pdm/
Dfsl_pdm.h983 base->VAD0_SCONFIG |= PDM_VAD0_SCONFIG_VADSFILEN_MASK; in PDM_EnableHwvadSignalFilter()
987 base->VAD0_SCONFIG &= ~PDM_VAD0_SCONFIG_VADSFILEN_MASK; in PDM_EnableHwvadSignalFilter()
Dfsl_pdm.c838 PDM_VAD0_SCONFIG_VADSFILEN_MASK; in PDM_SetHwvadSignalFilterConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h43241 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
43247 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h43239 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
43245 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h43239 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
43245 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h34752 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
34758 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
DMIMXRT735S_cm33_core1.h34812 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
34818 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
DMIMXRT735S_ezhv.h49995 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
50001 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
DMIMXRT735S_cm33_core0.h50019 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
50025 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h43241 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
43247 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h43241 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
43247 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h43239 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
43245 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
DMIMX8MN6_ca53.h43253 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
43259 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h37609 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
37615 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
DMIMXRT758S_hifi1.h37547 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
37553 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
DMIMXRT758S_cm33_core0.h52818 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
52824 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h37547 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
37553 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
DMIMXRT798S_cm33_core1.h37609 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
37615 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
DMIMXRT798S_hifi4.h52733 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
52739 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
DMIMXRT798S_cm33_core0.h52818 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
52824 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h59991 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
59997 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
DMIMXRT1175_cm7.h59089 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
59095 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h58565 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
58571 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
DMIMXRT1165_cm4.h59467 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
59473 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h59089 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) macro
59095 …(uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)

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