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Searched refs:PDM_FIFO_STAT_FIFOOVF6_MASK (Results 1 – 25 of 68) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/pdm/
Dfsl_pdm.h119 kPDM_FifoStatusOverflowCh6 = PDM_FIFO_STAT_FIFOOVF6_MASK, /*!< channel6 fifo status overflow */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h42716 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
42722 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h42714 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
42720 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h42714 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
42720 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h34020 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
34026 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
DMIMXRT735S_cm33_core1.h34080 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
34086 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
DMIMXRT735S_ezhv.h49263 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
49269 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
DMIMXRT735S_cm33_core0.h49287 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
49293 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h42716 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
42722 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h42716 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
42722 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h42714 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
42720 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
DMIMX8MN6_ca53.h42728 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
42734 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h36877 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
36883 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
DMIMXRT758S_hifi1.h36815 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
36821 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
DMIMXRT758S_cm33_core0.h52086 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
52092 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h36815 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
36821 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
DMIMXRT798S_cm33_core1.h36877 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
36883 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
DMIMXRT798S_hifi4.h52001 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
52007 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
DMIMXRT798S_cm33_core0.h52086 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
52092 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h59482 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
59488 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
DMIMXRT1175_cm7.h58580 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
58586 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h58056 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
58062 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
DMIMXRT1165_cm4.h58958 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
58964 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h58580 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
58586 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h61211 #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) macro
61217 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)

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