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Searched refs:PDM_FIFO_STAT_FIFOOVF5_MASK (Results 1 – 25 of 68) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/pdm/
Dfsl_pdm.h118 kPDM_FifoStatusOverflowCh5 = PDM_FIFO_STAT_FIFOOVF5_MASK, /*!< channel5 fifo status overflow */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h42708 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
42714 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h42706 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
42712 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h42706 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
42712 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h34012 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
34018 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
DMIMXRT735S_cm33_core1.h34072 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
34078 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
DMIMXRT735S_ezhv.h49255 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
49261 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
DMIMXRT735S_cm33_core0.h49279 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
49285 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h42708 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
42714 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h42708 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
42714 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h42706 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
42712 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
DMIMX8MN6_ca53.h42720 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
42726 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h36869 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
36875 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
DMIMXRT758S_hifi1.h36807 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
36813 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
DMIMXRT758S_cm33_core0.h52078 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
52084 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h36807 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
36813 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
DMIMXRT798S_cm33_core1.h36869 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
36875 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
DMIMXRT798S_hifi4.h51993 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
51999 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
DMIMXRT798S_cm33_core0.h52078 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
52084 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h59474 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
59480 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
DMIMXRT1175_cm7.h58572 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
58578 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h58048 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
58054 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
DMIMXRT1165_cm4.h58950 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
58956 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h58572 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
58578 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h61203 #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) macro
61209 … (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)

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