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Searched refs:PCIE_CTRL2_IRQn (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h166 PCIE_CTRL2_IRQn = 80, /**< Channels [63:32] interrupts requests */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h166 PCIE_CTRL2_IRQn = 80, /**< Channels [63:32] interrupts requests */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h166 PCIE_CTRL2_IRQn = 80, /**< Channels [63:32] interrupts requests */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h166 PCIE_CTRL2_IRQn = 80, /**< Channels [63:32] interrupts requests */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h166 PCIE_CTRL2_IRQn = 80, /**< Channels [63:32] interrupts requests */ enumerator
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h244 …PCIE_CTRL2_IRQn = 123, /**< Coming from GLUE logic, of set / reset FF, … enumerator