Home
last modified time | relevance | path

Searched refs:OTPC_TIMING1_TPD_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h42555 #define OTPC_TIMING1_TPD_MASK (0xFF000000U) macro
42558 … (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h42525 #define OTPC_TIMING1_TPD_MASK (0xFF000000U) macro
42528 … (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h53382 #define OTPC_TIMING1_TPD_MASK (0xFF000000U) macro
53385 … (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK)
DMCXN546_cm33_core1.h53382 #define OTPC_TIMING1_TPD_MASK (0xFF000000U) macro
53385 … (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h53382 #define OTPC_TIMING1_TPD_MASK (0xFF000000U) macro
53385 … (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK)
DMCXN547_cm33_core1.h53382 #define OTPC_TIMING1_TPD_MASK (0xFF000000U) macro
53385 … (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h54117 #define OTPC_TIMING1_TPD_MASK (0xFF000000U) macro
54120 … (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK)
DMCXN947_cm33_core0.h54117 #define OTPC_TIMING1_TPD_MASK (0xFF000000U) macro
54120 … (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h54117 #define OTPC_TIMING1_TPD_MASK (0xFF000000U) macro
54120 … (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK)
DMCXN946_cm33_core1.h54117 #define OTPC_TIMING1_TPD_MASK (0xFF000000U) macro
54120 … (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK)