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Searched refs:OSCCA_SAFO_SGI_CTRL2_INCR_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h51244 #define OSCCA_SAFO_SGI_CTRL2_INCR_MASK (0x8U) macro
51247 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_INCR_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_INCR_MASK)
DMIMXRT798S_cm33_core0.h51327 #define OSCCA_SAFO_SGI_CTRL2_INCR_MASK (0x8U) macro
51330 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_INCR_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_INCR_MASK)
DMIMXRT798S_ezhv.h51294 #define OSCCA_SAFO_SGI_CTRL2_INCR_MASK (0x8U) macro
51297 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_INCR_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_INCR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h48532 #define OSCCA_SAFO_SGI_CTRL2_INCR_MASK (0x8U) macro
48535 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_INCR_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_INCR_MASK)
DMIMXRT735S_cm33_core0.h48528 #define OSCCA_SAFO_SGI_CTRL2_INCR_MASK (0x8U) macro
48531 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_INCR_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_INCR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h51327 #define OSCCA_SAFO_SGI_CTRL2_INCR_MASK (0x8U) macro
51330 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_INCR_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_INCR_MASK)
DMIMXRT758S_ezhv.h51270 #define OSCCA_SAFO_SGI_CTRL2_INCR_MASK (0x8U) macro
51273 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_INCR_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_INCR_MASK)