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Searched refs:OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h51274 #define OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK (0x400000U) macro
51277 …(uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK)
DMIMXRT798S_cm33_core0.h51357 #define OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK (0x400000U) macro
51360 …(uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK)
DMIMXRT798S_ezhv.h51324 #define OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK (0x400000U) macro
51327 …(uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h48562 #define OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK (0x400000U) macro
48565 …(uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK)
DMIMXRT735S_cm33_core0.h48558 #define OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK (0x400000U) macro
48561 …(uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h51357 #define OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK (0x400000U) macro
51360 …(uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK)
DMIMXRT758S_ezhv.h51300 #define OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK (0x400000U) macro
51303 …(uint32_t)(x)) << OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_SHIFT)) & OSCCA_SAFO_SGI_CTRL2_BYTES_ORDER_MASK)