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Searched refs:OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h51406 #define OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK (0x10000000U) macro
51409 …2_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_HAS_SM3_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK)
DMIMXRT798S_cm33_core0.h51489 #define OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK (0x10000000U) macro
51492 …2_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_HAS_SM3_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK)
DMIMXRT798S_ezhv.h51456 #define OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK (0x10000000U) macro
51459 …2_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_HAS_SM3_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h48694 #define OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK (0x10000000U) macro
48697 …2_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_HAS_SM3_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK)
DMIMXRT735S_cm33_core0.h48690 #define OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK (0x10000000U) macro
48693 …2_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_HAS_SM3_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h51489 #define OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK (0x10000000U) macro
51492 …2_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_HAS_SM3_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK)
DMIMXRT758S_ezhv.h51432 #define OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK (0x10000000U) macro
51435 …2_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_HAS_SM3_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_HAS_SM3_MASK)