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Searched refs:OSCCA_SAFO_SGI_CONFIG_EDC_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h51376 #define OSCCA_SAFO_SGI_CONFIG_EDC_MASK (0x200000U) macro
51379 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_EDC_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_EDC_MASK)
DMIMXRT798S_cm33_core0.h51459 #define OSCCA_SAFO_SGI_CONFIG_EDC_MASK (0x200000U) macro
51462 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_EDC_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_EDC_MASK)
DMIMXRT798S_ezhv.h51426 #define OSCCA_SAFO_SGI_CONFIG_EDC_MASK (0x200000U) macro
51429 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_EDC_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_EDC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h48664 #define OSCCA_SAFO_SGI_CONFIG_EDC_MASK (0x200000U) macro
48667 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_EDC_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_EDC_MASK)
DMIMXRT735S_cm33_core0.h48660 #define OSCCA_SAFO_SGI_CONFIG_EDC_MASK (0x200000U) macro
48663 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_EDC_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_EDC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h51459 #define OSCCA_SAFO_SGI_CONFIG_EDC_MASK (0x200000U) macro
51462 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_EDC_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_EDC_MASK)
DMIMXRT758S_ezhv.h51402 #define OSCCA_SAFO_SGI_CONFIG_EDC_MASK (0x200000U) macro
51405 …(((uint32_t)(((uint32_t)(x)) << OSCCA_SAFO_SGI_CONFIG_EDC_SHIFT)) & OSCCA_SAFO_SGI_CONFIG_EDC_MASK)